专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06564237B2 Arithmetic unit and data processing unit 失效
公开(公告)号：US06564237B2
公开(公告)日：2003-05-13
申请号：US09978204
申请日：2001-10-17
申请人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
发明人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
IPC分类号： G06F738
CPC分类号： H03M7/4006 , G06F7/02 , G06F2207/025 , H03M7/46
摘要： For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.

2. 发明授权

US06332152B1 Arithmetic unit and data processing unit 失效
标题翻译：算术单元和数据处理单元
公开(公告)号：US06332152B1
公开(公告)日：2001-12-18
申请号：US09201720
申请日：1998-11-30
申请人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
发明人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
IPC分类号： G06F738
CPC分类号： H03M7/4006 , G06F7/02 , G06F2207/025 , H03M7/46
摘要： For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.
摘要翻译：对于每个数据，连续发生的数据匹配数量与非匹配数据一起写入存储器，并且读出来自存储器的数据以连续执行后续数据处理，同时检测写入到记忆。为了实现这一点，在数据寄存器中设置期望值，并且发出比较指令，通过该比较指令将寄存器中设置的值与在第二寄存器中设置的值进行比较，并且连续发生的匹配次数一起输出具有不匹配的数据; 在检索计数器的输出达到预定值的情况下，比较指令被终止，因此连续匹配的数量，非匹配数据和结束标志信号被写入同一地址的存储器。

3. 发明授权

US5999654A Image processor capable of transferring image data from an input buffer to memory at a high rate of speed 失效
标题翻译：图像处理器能够以高速率将图像数据从输入缓冲器传送到存储器
公开(公告)号：US5999654A
公开(公告)日：1999-12-07
申请号：US895615
申请日：1997-07-16
申请人： Masayoshi Toujima , Yasuo Kohashi , Hitoshi Fujimoto , Tomonori Yonezawa , Masatoshi Matsuo , Shunichi Kurohmaru
发明人： Masayoshi Toujima , Yasuo Kohashi , Hitoshi Fujimoto , Tomonori Yonezawa , Masatoshi Matsuo , Shunichi Kurohmaru
IPC分类号： G06T1/60 , G06K9/36
CPC分类号： G06T1/60
摘要： A bus switch is connected among an input buffer memory, a data memory, and an encoding unit, to select between a first bus connection of the input buffer memory and the data memory and a second bus connection of the data memory and the encoding unit. A data transfer control unit controls the bus switch to select the first bus connection in response to a data request signal from the encoding unit, controls the process of reading from the input buffer memory and the process of writing into the data memory, controls the bus switch to select the second bus connection upon completion of the transfer of one unit of image data, and sends a transfer completion signal in order of causing the encoding unit to start performing encoding processing. This makes it possible to transfer image data from the input buffer memory to the data memory at high speed.
摘要翻译：在输入缓冲存储器，数据存储器和编码单元之间连接总线开关，以在输入缓冲存储器的第一总线连接和数据存储器之间选择数据存储器和编码单元的第二总线连接。数据传输控制单元响应于来自编码单元的数据请求信号控制总线开关选择第一总线连接，控制从输入缓冲存储器读取的处理和写入数据存储器的处理，控制总线切换到在完成一个单位图像数据的传送时选择第二总线连接，并且按照编码单元开始执行编码处理的顺序发送传送完成信号。这使得可以高速地将图像数据从输入缓冲存储器传送到数据存储器。

4. 发明授权

US06671708B1 Processor and image processing device 有权
标题翻译：处理器和图像处理设备
公开(公告)号：US06671708B1
公开(公告)日：2003-12-30
申请号：US09600247
申请日：2000-08-31
申请人： Shunichi Kuromaru , Mana Hamada , Tomonori Yonezawa , Masatoshi Matsuo , Tsuyoshi Nakamura , Masahiro Oohashi
发明人： Shunichi Kuromaru , Mana Hamada , Tomonori Yonezawa , Masatoshi Matsuo , Tsuyoshi Nakamura , Masahiro Oohashi
IPC分类号： G06F738
CPC分类号： G06F9/3885 , G06F9/30036 , G06F17/10 , G06T1/20
摘要： An image processing apparatus according to the present invention comprises a general arithmetic circuit 101 comprising a program control circuit 103, a first address generator 104, a first data memory 105, a first pipeline operation circuit 106, a second address generator 113, a second data memory 114 and a second pipeline operation circuit 112, and a dedicated arithmetic circuit 102 comprising a control circuit 115, a first dedicated pipeline operation circuit 107, a second dedicated pipeline operation circuit 108, . . . , an N-th dedicated pipeline operation circuit 110, as shown in FIG. 1. The arithmetic unit having the above-described structure, for example, can realize an arithmetic unit which can be applied to various applications. Further, considering the age of IP (Intellectual Property) which will come in the future, the arithmetic unit can exhibit the flexibility toward the applications.
摘要翻译：根据本发明的图像处理装置包括通用运算电路101，其包括程序控制电路103，第一地址生成器104，第一数据存储器105，第一流水线运算电路106，第二地址发生器113，第二数据存储器114和第二流水线操作电路112，以及专用运算电路102，包括控制电路115，第一专用流水线运行电路107，第二专用流水线运行电路108。。。，第N专用流水线运算电路110，如图1所示。例如，具有上述结构的运算单元可以实现可应用于各种应用的算术单元。此外，考虑到将来会出现的知识产权（知识产权）的年龄，算术单位可以展现出应用的灵活性。

5. 发明授权

US07089431B2 Data processing system for reducing wasteful power consumption 有权
标题翻译：用于减少浪费电力消耗的数据处理系统
公开(公告)号：US07089431B2
公开(公告)日：2006-08-08
申请号：US10352850
申请日：2003-01-29
申请人： Masatoshi Matsuo , Youichi Nishida , Takashi Hashimoto , Masahiro Ohashi , Hiroto Tomita
发明人： Masatoshi Matsuo , Youichi Nishida , Takashi Hashimoto , Masahiro Ohashi , Hiroto Tomita
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , Y02D10/128 , Y02D10/159 , Y02D10/171
摘要： An image processing unit decodes coded data that have been coded and synthesizes the decoded moving image with graphics data. In a case where only graphics data are to be displayed, a bypass unit outputs the graphics data to a display device without use of an image processing unit. A control unit performs control of the supplying of a power supply voltage and a clock to a region containing the image processing unit and performs control of the bypass unit. If processing at the image processing unit is unnecessary, the supply of a power supply voltage or the supply of a clock to the region containing the image processing unit is stopped so as to stop the region and enable reduction of wasteful power consumption.
摘要翻译：图像处理单元对已编码的编码数据进行解码，并用图形数据合成解码的运动图像。在仅显示图形数据的情况下，旁路单元将图形数据输出到显示装置，而不使用图像处理单元。控制单元执行向包含图像处理单元的区域提供电源电压和时钟的控制，并执行旁路单元的控制。如果不需要图像处理单元的处理，则停止向包含图像处理单元的区域提供电源电压或提供时钟，以便停止该区域并且能够减少浪费的功率消耗。

6. 发明授权

US07350035B2 Information-processing apparatus and electronic equipment using thereof 失效
标题翻译：信息处理装置及其使用的电子设备
公开(公告)号：US07350035B2
公开(公告)日：2008-03-25
申请号：US10902805
申请日：2004-08-02
申请人： Hiroto Tomita , Masatoshi Matsuo
发明人： Hiroto Tomita , Masatoshi Matsuo
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F15/7842 , G06F15/8007
摘要： An information-processing apparatus comprises a motion-detecting unit, a motion-compensating unit, a DCT/IDCT unit, a Q/IQ unit, a VLC unit, a VLD unit, and a DSP unit, as a plurality of units. A mode-controlling unit can utilize at least two modes of used of the information-processing apparatus. One mode is a “process mode ” where the processing of moving picture are performed, and another mode is a “memory mode” where all internal memories of the plurality of processing units are logically combined to be directly accessible from the outside as one memory via an interface unit.
摘要翻译：作为多个单元，信息处理装置包括运动检测单元，运动补偿单元，DCT / IDCT单元，Q / IQ单元，VLC单元，VLD单元和DSP单元。模式控制单元可以利用信息处理装置中使用的至少两种模式。一种模式是执行运动图像的处理的“处理模式”，另一模式是“存储模式”，其中多个处理单元的所有内部存储器被逻辑组合以从外部直接访问作为一个存储器经由接口单元。

7. 发明申请

US20050033927A1 Information-processing apparatus and electronic equipment using thereof 失效
标题翻译：信息处理装置及其使用的电子设备
公开(公告)号：US20050033927A1
公开(公告)日：2005-02-10
申请号：US10902805
申请日：2004-08-02
申请人： Hiroto Tomita , Masatoshi Matsuo
发明人： Hiroto Tomita , Masatoshi Matsuo
IPC分类号： G06F12/06 , G06F12/00 , G06F13/00 , G06F13/16 , G06F15/78 , G06F15/80 , H04M1/00 , H04N5/00 , H04N5/232 , H04N5/765 , H04N101/00
CPC分类号： G06F15/7842 , G06F15/8007
摘要： An information-processing apparatus comprises a motion-detecting unit, a motion-compensating unit, a DCT/IDCT unit, a Q/IQ unit, a VLC unit, a VLD unit, and a DSP unit, as a plurality of processing units. Thanks to control of a mode-controlling unit, two modes can be used. One of them is an “operation mode” where processes of moving picture are performed, and the other of them is a “memory mode” where all internal memories of the plurality of processing units are logically combined to be directly accessible from the outside as one memory via an interface unit.
摘要翻译：作为多个处理单元，信息处理装置包括运动检测单元，运动补偿单元，DCT / IDCT单元，Q / IQ单元，VLC单元，VLD单元和DSP单元。由于模式控制单元的控制，可以使用两种模式。其中之一是执行运动图像处理的“操作模式”，而另一个是“存储器模式”，其中多个处理单元的所有内部存储器被逻辑组合以从外部直接访问作为一个存储器通过接口单元。

8. 发明申请

US20100013930A1 VIDEO DISPLAY APPARATUS AND VIDEO DISPLAY METHOD 审中-公开
标题翻译：视频显示设备和视频显示方法
公开(公告)号：US20100013930A1
公开(公告)日：2010-01-21
申请号：US12438785
申请日：2007-10-04
申请人： Masatoshi Matsuo , Ikuo Fuchigami
发明人： Masatoshi Matsuo , Ikuo Fuchigami
IPC分类号： H04N7/18
CPC分类号： B60R1/00 , B60R2300/105 , B60R2300/302 , B60R2300/303 , B60R2300/605 , B60R2300/70 , B60R2300/8026 , B60R2300/804 , B60R2300/806 , G06T3/0075 , G06T11/00 , H04N7/181
摘要： A video display apparatus for displaying on a monitor videos captured using capturing sections is provided. The capturing sections (101a-101n) capture the periphery of a vehicle. Reference position setting sections (102a-102n) set a focus monitor position as a video construction reference position. A steering angle detecting section (108) detects a steering angle caused by a driver's operation. The video construction reference position is corrected based on the steering angle. After video construction reference position information adding sections (103a-103n) add video construction reference position information to the videos, a video constructing section (104) combines the videos of the capturing sections so that all of the video construction reference positions overlap each other. A display video generating section (106) clips a video based on a display area specified by a display area specifying section (105). A video display section (107) outputs the clipped video to the monitor for display.
摘要翻译：提供一种用于在监视器上显示使用捕获部分捕获的视频的视频显示装置。捕获部（101a-101n）捕获车辆的周边。基准位置设定部（102a-102n）将焦点监视位置设定为视频构造基准位置。转向角检测部（108）检测由驾驶员的操作引起的转向角。基于转向角校正视频构造基准位置。在视频构建参考位置信息添加部分（103a-103n）之后，将视频构造参考位置信息添加到视频中，视频构建部分（104）组合拍摄部分的视频，使得所有视频构造参考位置彼此重叠。显示视频生成部（106）基于由显示区域指定部（105）指定的显示区域来剪辑视频。视频显示部分（107）将剪辑的视频输出到监视器以进行显示。

9. 发明授权

US06731293B2 Image output device and image output control method 失效
标题翻译：图像输出设备和图像输出控制方式
公开(公告)号：US06731293B2
公开(公告)日：2004-05-04
申请号：US09867708
申请日：2001-05-31
申请人： Masayoshi Tojima , Toshihiro Moriiwa , Masatoshi Matsuo
发明人： Masayoshi Tojima , Toshihiro Moriiwa , Masatoshi Matsuo
IPC分类号： G06F1300
CPC分类号： G09G5/393 , G09G5/18 , G09G5/397 , G09G2340/0407
摘要： The present invention provides an image output device which can periodically update display of image data as well as update the display images immediately and with minimum data transfer. A data transfer request control circuit 107 including a frame rate register 108 for deciding a data transfer request issue cycle and a data transfer request issuing unit 109 is provided in a video processing unit 104 of the image output device. When an update flag is set in the frame rate register 108, the data transfer request is issued in the next transfer section, regardless of the periodic transfer cycle, and the image data stored in the frame memory 106 are update.
摘要翻译：本发明提供一种可以周期性地更新图像数据的显示以及立即更新显示图像并且以最小的数据传送的图像输出装置。包括用于决定数据传送请求发布周期的帧速率寄存器108和数据传送请求发布单元109的数据传送请求控制电路107被提供在图像输出设备的视频处理单元104中。当在帧速率寄存器108中设置更新标志时，无论周期性传送周期如何，都在下一个传送部分中发出数据传送请求，并且更新存储在帧存储器106中的图像数据。

10. 发明授权

US08426511B2 Cationic polyurethane resin aqueous dispersion, ink-jet receiving agent including the same, and ink-jet recording medium using the same 有权
标题翻译：阳离子聚氨酯树脂水性分散体，包含该阳离子聚氨酯树脂的水分散体的喷墨接收剂和使用其的喷墨记录介质
公开(公告)号：US08426511B2
公开(公告)日：2013-04-23
申请号：US13064977
申请日：2011-04-29
申请人： Kenji Nagao , Kazunori Tanaka , Masato Inoue , Masatoshi Matsuo
发明人： Kenji Nagao , Kazunori Tanaka , Masato Inoue , Masatoshi Matsuo
IPC分类号： B05D3/02 , B41M5/00 , B41M5/40 , C08G18/00 , C08G18/08 , C08G18/28 , C08G18/70 , C08K3/10 , C08K3/20 , C08L75/00
CPC分类号： C08G18/44 , B41M5/5245 , B41M5/5281 , C08G18/0814 , C08G18/12 , C08G18/289 , C08G18/3819 , C08G18/4202 , C08G18/4825 , C08G18/5069 , C08G18/758 , C09D11/30 , C09D175/04 , C08G18/3228
摘要： A cationic polyurethane resin aqueous dispersion wherein a cationic polyurethane resin (B) including a structural unit (A) represented by the following general formula (I) is dispersed in aqueous medium, and the content of a cationic amino group of the structural unit (A) in the cationic polyurethane resin (B) is 0.005 to 1.5 equivalents/kg. (In the formula, R1 represents an alkylene group which may include an alicyclic structure, a residue of bivalent phenol or polyoxyalkylene group, R2 and R3 each independently represents an alkyl group which may include an alicyclic structure, and R4 represents a hydrogen atom or a residue of the quaternizing agent which is introduced by the quaternizing reaction, and X− represents an anionic counter ion.)
摘要翻译：将含有下述通式（I）表示的结构单元（A）的阳离子性聚氨酯树脂（B））分散在水性介质中的阳离子型聚氨酯树脂水分散体，其结构单元（A ）为0.005〜1.5当量/ kg。（式中，R1表示可以包含脂环结构的亚烷基，二价苯酚或聚氧化烯基的残基，R2和R3各自独立地表示可以包含脂环结构的烷基，R4表示氢原子或通过季铵化反应引入的季铵化剂的残基，X-表示阴离子抗衡离子。）

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式