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1. 发明授权

US07062633B1 Conditional vector arithmetic method and conditional vector arithmetic unit 失效
标题翻译：条件向量算法和条件向量运算单元
公开(公告)号：US07062633B1
公开(公告)日：2006-06-13
申请号：US09868048
申请日：1999-12-15
申请人： Mana Hamada , Shunichi Kuromaru , Tomonori Yonezawa , Tsuyoshi Nakamura
发明人： Mana Hamada , Shunichi Kuromaru , Tomonori Yonezawa , Tsuyoshi Nakamura
IPC分类号： G06F9/302 , G06F9/38
CPC分类号： G06F17/16
摘要： It is decided whether a first source data from the memory 101 is a data which is to be subjected to arithmetic or not by a state flag detection means 150, the result of the decision is retained as a state flag, and it is decided by a condition decision means 109 whether or not the state flag satisfies a condition for performing the arithmetic. A control means 110 controls whether an ALU 100 should perform the arithmetic or not on the basis of the condition satisfaction/dissatisfaction information.
摘要翻译：决定来自存储器101的第一源数据是否是由状态标志检测装置150进行算术的数据，判定结果被保留为状态标志，并且由条件判定单元109，判断状态标志是否满足进行运算的条件。控制装置110基于条件满足/不满意信息来控制ALU 100是否应该执行算术。

2. 发明授权

US06671708B1 Processor and image processing device 有权
标题翻译：处理器和图像处理设备
公开(公告)号：US06671708B1
公开(公告)日：2003-12-30
申请号：US09600247
申请日：2000-08-31
申请人： Shunichi Kuromaru , Mana Hamada , Tomonori Yonezawa , Masatoshi Matsuo , Tsuyoshi Nakamura , Masahiro Oohashi
发明人： Shunichi Kuromaru , Mana Hamada , Tomonori Yonezawa , Masatoshi Matsuo , Tsuyoshi Nakamura , Masahiro Oohashi
IPC分类号： G06F738
CPC分类号： G06F9/3885 , G06F9/30036 , G06F17/10 , G06T1/20
摘要： An image processing apparatus according to the present invention comprises a general arithmetic circuit 101 comprising a program control circuit 103, a first address generator 104, a first data memory 105, a first pipeline operation circuit 106, a second address generator 113, a second data memory 114 and a second pipeline operation circuit 112, and a dedicated arithmetic circuit 102 comprising a control circuit 115, a first dedicated pipeline operation circuit 107, a second dedicated pipeline operation circuit 108, . . . , an N-th dedicated pipeline operation circuit 110, as shown in FIG. 1. The arithmetic unit having the above-described structure, for example, can realize an arithmetic unit which can be applied to various applications. Further, considering the age of IP (Intellectual Property) which will come in the future, the arithmetic unit can exhibit the flexibility toward the applications.
摘要翻译：根据本发明的图像处理装置包括通用运算电路101，其包括程序控制电路103，第一地址生成器104，第一数据存储器105，第一流水线运算电路106，第二地址发生器113，第二数据存储器114和第二流水线操作电路112，以及专用运算电路102，包括控制电路115，第一专用流水线运行电路107，第二专用流水线运行电路108。。。，第N专用流水线运算电路110，如图1所示。例如，具有上述结构的运算单元可以实现可应用于各种应用的算术单元。此外，考虑到将来会出现的知识产权（知识产权）的年龄，算术单位可以展现出应用的灵活性。

3. 发明授权

US06662288B1 Address generating apparatus and motion vector detector 有权
标题翻译：地址生成装置和运动矢量检测器
公开(公告)号：US06662288B1
公开(公告)日：2003-12-09
申请号：US09856775
申请日：2001-06-27
申请人： Mana Hamada , Shunichi Kuromaru , Tomonori Yonezawa
发明人： Mana Hamada , Shunichi Kuromaru , Tomonori Yonezawa
IPC分类号： G06F1208
CPC分类号： G06F3/0485 , G06F9/345 , G06F9/3455 , G06T7/238 , G06T2207/10016 , H04N19/433 , H04N19/51
摘要： A high-function address generating apparatus is realized which generates a memory address that can access a multidimensional area without running over a memory area specified by a user. Continuous addressing domain which is determined by a top address and a final address is set by an addressing domain setting means 101, an address is generated by a two-dimensional address generating means 106, the address in a two-dimensional area is compared with the final address and the top address by a first and a second comparing means 108 and 109, respectively, whether it runs over the addressing domain or not is judged by an address correction means 112, and an address running over is corrected so as to not run over.
摘要翻译：实现了高功能地址生成装置，其产生可以访问多维区域而不在用户指定的存储区域上运行的存储器地址。由寻址域设置装置101设置由顶部地址和最终地址确定的连续寻址域，由二维地址生成装置106产生地址，将二维区域中的地址与分别由第一和第二比较装置108和109分别确定地址是否通过寻址域运行的最终地址和顶部地址由地址校正装置112判断，并且运行的地址被校正以便不运行过度。

4. 发明授权

US06791625B1 Video processing apparatus for performing address generation and control, and method therefor 失效
标题翻译：用于执行地址产生和控制的视频处理装置及其方法
公开(公告)号：US06791625B1
公开(公告)日：2004-09-14
申请号：US09868183
申请日：2001-07-12
申请人： Yasuo Kohashi , Toshihiro Moriiwa , Shunichi Kuromaru , Hiromasa Nakajima , Tomonori Yonezawa , Miki Arita
发明人： Yasuo Kohashi , Toshihiro Moriiwa , Shunichi Kuromaru , Hiromasa Nakajima , Tomonori Yonezawa , Miki Arita
IPC分类号： H04N964
CPC分类号： H04N19/43 , H04N19/423 , H04N19/51 , H04N19/61
摘要： Apparatus and method for data transmission while performing encoding processing on a non-limited moving vector mode, which avoids an increase in required memory capacity and a reduction in processing load, the apparatus comprising a two dimensional address generating unit for generating an access address of an external memory and an address control unit for administrating the horizontal position and the vertical position of the extended logical space and generating an operation authorizing signal for the two dimensional address generating unit, and the two dimensional address generating unit and the address control unit are operated in relation to each other so that an access address to outside the effective video data region is controlled to be an address of a pixel data at the periphery of the effective video data region, thereby reducing the extended region in the external memory.
摘要翻译：在对非限制的移动矢量模式进行编码处理时进行数据传输的装置和方法，其避免所需存储器容量的增加和处理负载的减少，所述装置包括二维地址生成单元，用于生成外部存储器和用于管理扩展逻辑空间的水平位置和垂直位置的地址控制单元，并且生成用于二维地址生成单元的操作授权信号，并且二维地址生成单元和地址控制单元在使得有效视频数据区域之外的访问地址被控制为有效视频数据区域的周边处的像素数据的地址，从而减少外部存储器中的扩展区域。

5. 发明授权

US06332152B1 Arithmetic unit and data processing unit 失效
标题翻译：算术单元和数据处理单元
公开(公告)号：US06332152B1
公开(公告)日：2001-12-18
申请号：US09201720
申请日：1998-11-30
申请人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
发明人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
IPC分类号： G06F738
CPC分类号： H03M7/4006 , G06F7/02 , G06F2207/025 , H03M7/46
摘要： For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.
摘要翻译：对于每个数据，连续发生的数据匹配数量与非匹配数据一起写入存储器，并且读出来自存储器的数据以连续执行后续数据处理，同时检测写入到记忆。为了实现这一点，在数据寄存器中设置期望值，并且发出比较指令，通过该比较指令将寄存器中设置的值与在第二寄存器中设置的值进行比较，并且连续发生的匹配次数一起输出具有不匹配的数据; 在检索计数器的输出达到预定值的情况下，比较指令被终止，因此连续匹配的数量，非匹配数据和结束标志信号被写入同一地址的存储器。

6. 发明授权

US06564237B2 Arithmetic unit and data processing unit 失效
公开(公告)号：US06564237B2
公开(公告)日：2003-05-13
申请号：US09978204
申请日：2001-10-17
申请人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
发明人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
IPC分类号： G06F738
CPC分类号： H03M7/4006 , G06F7/02 , G06F2207/025 , H03M7/46
摘要： For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.

7. 发明授权

US07577557B2 Simulator and simulation method for behaviors of processors 失效
标题翻译：处理器行为的模拟器和仿真方法
公开(公告)号：US07577557B2
公开(公告)日：2009-08-18
申请号：US10969027
申请日：2004-10-21
申请人： Takahiro Kondo , Tsuyoshi Nakamura , Maiko Taruki , Tomonori Yonezawa
发明人： Takahiro Kondo , Tsuyoshi Nakamura , Maiko Taruki , Tomonori Yonezawa
IPC分类号： G06F17/50 , G06F9/44
CPC分类号： G06F17/5022
摘要： A simulator operable to simulate behaviors of a processor using software is provided. The simulator includes a command input unit, a memory element, a register element, a control element, a resource information storage unit, and a resource access-analyzing unit. The command input unit is operable to analyze/process entered commands. The memory element is operable to store executive instructions issued by the processor and data treated by the processor. The register element is operable to contain data for use in calculation. The control element is operable to access the memory element and register element in accordance with the executive instructions. The resource information storage unit is operable to contain specified resource information and a piece of read/write information for each piece of the resource information. The resource access-analyzing unit is operable to compare access destinations (the memory element and register element to be accessed by the control element) and a read/write classification with the resource information and read/write information contained in the resource information storage unit, thereby practicing a resource access analysis as to whether or not the access destinations are allowed by the resource information and read/write information.
摘要翻译：提供了一种可以使用软件模拟处理器行为的模拟器。模拟器包括命令输入单元，存储元件，寄存器元件，控制元件，资源信息存储单元和资源访问分析单元。命令输入单元用于分析/处理输入的命令。存储元件可操作以存储处理器发出的执行指令和由处理器处理的数据。寄存器元件可操作地包含用于计算的数据。控制元件可操作以根据执行指令访问存储器元件和寄存器元件。资源信息存储单元可操作以对于每个资源信息包含指定的资源信息和一条读/写信息。资源访问分析单元可操作以将资源信息存储单元中包含的资源信息和读取/写入信息的访问目的地（由控制元素访问的存储元件和注册元素）与读/写分类进行比较，从而对资源信息和读/写信息是否允许访问目的地进行资源访问分析。

8. 发明授权

US06513146B1 Method of designing semiconductor integrated circuit device, method of analyzing power consumption of circuit and apparatus for analyzing power consumption 有权
标题翻译：设计半导体集成电路器件的方法，分析电路功耗的方法和功耗分析仪器
公开(公告)号：US06513146B1
公开(公告)日：2003-01-28
申请号：US09711885
申请日：2000-11-15
申请人： Tomonori Yonezawa , Takayuki Sasaki , Takahiro Kondo , Hiroki Otsuki , Tsuyoshi Nakamura
发明人： Tomonori Yonezawa , Takayuki Sasaki , Takahiro Kondo , Hiroki Otsuki , Tsuyoshi Nakamura
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/78
摘要： The processing quantity of each description part is estimated through a source code analysis of a system operation description language or through simulation, or power consumption of each function is estimated through an operation description analysis of functions. Predetermined threshold values are set with respect to the processing quantity and the power consumption of each description part or function, so as to determine S/W and H/W implementation, and then, S/W and H/W partitioning is carried out. Thereafter, it is determined whether or not the total processing quantity or the total power consumption satisfies a desired design condition. Also, the S/W and H/W partitioning can be adjusted again in comprehensive consideration of the power consumption and the processing quantity, and the accuracy in the S/W and H/W partitioning can be improved by providing an instruction set simulator with a function to analyze power consumption. Moreover, an interface between S/W and H/W can be generated in the S/W and H/W partitioning so as to be automatically inserted into a S/W implemented part or a H/W implemented part.
摘要翻译：每个描述部分的处理量通过系统操作描述语言的源代码分析或通过仿真来估计，或者通过功能的操作描述分析来估计每个功能的功耗。相对于每个描述部分或功能的处理量和功耗来设置预定阈值，以便确定S / W和H / W实现，然后执行S / W和H / W分区。此后，确定总处理量或总功耗是否满足期望的设计条件。此外，可以综合考虑功耗和处理量来再次调整S / W和H / W分区，并且可以通过提供一个指令集模拟器来提高S / W和H / W分区的精度分析功耗的功能。此外，可以在S / W和H / W分区中产生S / W和H / W之间的接口，以便自动插入到S / W实现部分或H / W实现部分。

9. 发明申请

US20050091028A1 Simulator and simulation method 失效
标题翻译：模拟器和仿真方法
公开(公告)号：US20050091028A1
公开(公告)日：2005-04-28
申请号：US10969027
申请日：2004-10-21
申请人： Takahiro Kondo , Tsuyoshi Nakamura , Maiko Taruki , Tomonori Yonezawa
发明人： Takahiro Kondo , Tsuyoshi Nakamura , Maiko Taruki , Tomonori Yonezawa
IPC分类号： G06F11/28 , G06F9/455 , G06F11/30 , G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： A simulator operable to simulate behaviors of a processor using software is provided. The simulator includes a command input unit, a memory element, a register element, a control element, a resource information storage unit, and a resource access-analyzing unit. The command input unit is operable to analyze/process entered commands. The memory element is operable to store executive instructions issued by the processor and data treated by the processor. The register element is operable to contain data for use in calculation. The control element is operable to access the memory element and register element in accordance with the executive instructions. The resource information storage unit is operable to contain specified resource information and a piece of read/write information for each piece of the resource information. The resource access-analyzing unit is operable to compare access destinations (the memory element and register element to be accessed by the control element) and a read/write classification with the resource information and read/write information contained in the resource information storage unit, thereby practicing a resource access analysis as to whether or not the access destinations are allowed by the resource information and read/write information.
摘要翻译：提供了一种可以使用软件模拟处理器行为的模拟器。模拟器包括命令输入单元，存储元件，寄存器元件，控制元件，资源信息存储单元和资源访问分析单元。命令输入单元用于分析/处理输入的命令。存储元件可操作以存储处理器发出的执行指令和由处理器处理的数据。寄存器元件可操作地包含用于计算的数据。控制元件可操作以根据执行指令访问存储器元件和寄存器元件。资源信息存储单元可操作以对于每个资源信息包含指定的资源信息和一条读/写信息。资源访问分析单元可操作以将资源信息存储单元中包含的资源信息和读取/写入信息的访问目的地（由控制元素访问的存储元件和注册元素）与读/写分类进行比较，从而对资源信息和读/写信息是否允许访问目的地进行资源访问分析。

10. 发明申请

US20050066093A1 Real-time processor system and control method 审中-公开
标题翻译：实时处理器系统和控制方法
公开(公告)号：US20050066093A1
公开(公告)日：2005-03-24
申请号：US10942893
申请日：2004-09-17
申请人： Ryuji Fuchikami , Tomonori Yonezawa , Yoichi Nishida
发明人： Ryuji Fuchikami , Tomonori Yonezawa , Yoichi Nishida
IPC分类号： G06F13/362 , G06F9/46 , G06F13/00 , G06F13/14 , G06F13/24 , G06F13/26 , G06F15/16
CPC分类号： G06F13/26 , G06F13/362
摘要： A real time processor system comprises: a bus arbiter; a plurality of calculating units, each having a processor and an interruption processing unit; a DMA controller; a plurality of priority registers; a memory; and an SCI. The bus arbiter comprises: a priority comparing unit; and a bus assignment unit. Each of the plurality of priority registers stores an I/O access priority value corresponding to each of the calculating units. Priority values are compared, and then right of I/O use is determined. The values of the plurality of priority registers are changed, thereby adaptively performing multiple interruption processing.
摘要翻译：实时处理器系统包括：总线仲裁器; 多个计算单元，每个具有处理器和中断处理单元; 一个DMA控制器多个优先级寄存器; 记忆和SCI。总线仲裁器包括：优先级比较单元; 和总线分配单元。多个优先级寄存器中的每一个存储对应于每个计算单元的I / O访问优先级值。比较优先级值，然后确定I / O使用权。改变多个优先级寄存器的值，从而自适应地执行多个中断处理。

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