专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20190196996A1 DYNAMICALLY DETERMINING MEMORY ACCESS BURST LENGTH 审中-公开
公开(公告)号：US20190196996A1
公开(公告)日：2019-06-27
申请号：US15851087
申请日：2017-12-21
申请人： Advanced Micro Devices, Inc.
发明人： Kedarnath Balakrishnan , Ravindra N. Bhargava , Guanhao Shen , James Raymond Magro , Kevin M. Brandl
IPC分类号： G06F13/30 , G06F13/16 , G06F3/06
CPC分类号： G06F13/30 , G06F3/061 , G06F3/0659 , G06F13/1642 , G06F13/1668
摘要： Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory read requests have been sent to a memory device in a read mode of a data bus, the memory controller determines a threshold number of memory write requests to send to the memory device in an upcoming write mode is a number of outstanding memory write requests. Alternatively, the memory controller determines the threshold number of memory write requests to send to the memory device in an upcoming write mode is a maximum value of the number of outstanding memory write requests and a programmable value of the write burst length stored in a control register. Therefore, the write burst length is determined dynamically. Similarly, the read burst length is determined dynamically when the write mode ends.

2. 发明授权

US09921985B2 Direct memory access controller 有权
公开(公告)号：US09921985B2
公开(公告)日：2018-03-20
申请号：US14860398
申请日：2015-09-21
申请人： Microchip Technology Incorporated
发明人： Joseph W. Triece , Rodney J. Pesavento , Gregg D. Lahti , Steven Dawson
IPC分类号： G06F13/28 , G06F13/00 , G06F13/34 , G06F13/30 , G06F13/16 , G06F13/40
CPC分类号： G06F13/34 , G06F13/1689 , G06F13/285 , G06F13/30 , G06F13/4022
摘要： A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

3. 发明申请

US20180052789A1 Direct Memory Access Transmission Control Method and Apparatus 审中-公开
公开(公告)号：US20180052789A1
公开(公告)日：2018-02-22
申请号：US15797605
申请日：2017-10-30
申请人： Huawei Technologies Co., Ltd.
发明人： Hao Chen , Huifeng Xu , Haitao Guo
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F7/74 , G06F7/76 , G06F7/78 , G06F9/5038 , G06F13/18 , G06F13/30 , G06F2213/2802
摘要： A direct memory access (DMA) transmission control method and apparatus, where the method includes selecting a target channel for the target DMA task according to a priority corresponding to the target DMA task when a DMA transmission request for transmitting data of a target DMA task is received, querying a task type and a priority of another DMA task that has occupied a channel and a task type of the target DMA task when the other DMA task exists on the DMA channel, comparing the task type and the priority of the other DMA task that has occupied the channel with the task type and the priority of the target DMA task, and controlling data transmission on the DMA channel according to a comparison result. Hence, the urgent DMA task can be preferentially processed.

4. 发明申请

US20170222790A1 CLOCK SUSTAIN IN THE ABSENCE OF A REFERENCE CLOCK IN A COMMUNICATION SYSTEM 审中-公开
公开(公告)号：US20170222790A1
公开(公告)日：2017-08-03
申请号：US15411801
申请日：2017-01-20
申请人： Analog Devices, Inc.
发明人： WILLIAM HOOPER , Lewis F. LAHR
IPC分类号： H04L7/00 , H04L7/02 , H04L12/40
CPC分类号： H04L7/0083 , G06F13/30 , G06F13/362 , H04H60/00 , H04J3/0647 , H04L7/04 , H04L12/40 , H04L12/403 , H04R5/00 , H04R2420/07 , H04R2460/03 , H04R2499/13
摘要： Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.

5. 发明授权

US09535826B2 Automatic communication and optimization of multi-dimensional arrays for many-core coprocessor using static compiler analysis 有权
标题翻译：使用静态编译器分析，为多核协处理器自动通信和优化多维数组
公开(公告)号：US09535826B2
公开(公告)日：2017-01-03
申请号：US14293667
申请日：2014-06-02
申请人： NEC Laboratories America, Inc.
发明人： Nishkam Ravi , Yi Yang , Srimat Chakradhar , Bin Ren
IPC分类号： G06F12/02 , G06F13/30 , G06F9/45 , G06F12/00
CPC分类号： G06F12/0207 , G06F8/41 , G06F8/443 , G06F8/51 , G06F12/023 , G06F13/30 , G06F2212/1016
摘要： There are provided source-to-source transformation methods for a multi-dimensional array and/or a multi-level pointer for a computer program. A method includes minimizing a number of holes for variable length elements for a given dimension of the array and/or pointer using at least two stride values included in stride buckets. The minimizing step includes modifying memory allocation sites, for the array and/or pointer, to allocate memory based on the stride values. The minimizing step further includes modifying a multi-dimensional memory access, for accessing the array and/or pointer, into a single dimensional memory access using the stride values. The minimizing step also includes inserting offload pragma for a data transfer of the array and/or pointer prior as at least one of a single-dimensional array and a single-level pointer. The data transfer is from a central processing unit to a coprocessor over peripheral component interconnect express.
摘要翻译：为计算机程序提供多维数组和/或多级指针的源到源转换方法。一种方法包括使用包括在步幅桶中的至少两个步幅值来最小化数组和/或指针的给定维度的可变长度元素的多个孔。最小化步骤包括修改针对阵列和/或指针的内存分配站点，以基于步幅值来分配存储器。最小化步骤还包括使用步幅值将用于访问阵列和/或指针的多维存储器访问修改为单维存储器访问。最小化步骤还包括在单维数组和单级指针中的至少一个之前插入用于数组和/或指针的数据传输的卸载pragma。数据传输是通过外围组件互连快递从中央处理单元到协处理器的。

6. 发明申请

US20160239443A1 DMA CONTROLLER 审中-公开
标题翻译： DMA控制器
公开(公告)号：US20160239443A1
公开(公告)日：2016-08-18
申请号：US15046389
申请日：2016-02-17
申请人： FANUC Corporation
发明人： Masahiro MIURA
IPC分类号： G06F13/30
CPC分类号： G06F13/30
摘要： A direct memory access (DMA) controller issues a standby request a predetermined period of time before data transfer having a high priority starts and prohibits data transfer having a low priority in advance, and thus data transfer having a high priority can generate a transfer cycle from a data transfer start point in time without waiting. Accordingly, a transfer time is reduced, a variation in the transfer time is reduced, and thus a real time property of a system is improved.
摘要翻译：直接存储器访问（DMA）控制器在具有高优先级的数据传输开始之前的预定时间段内发出待机请求，并且预先禁止具有低优先级的数据传输，因此具有高优先级的数据传输可以产生从数据传输起始点，无需等待。因此，传输时间减少，传输时间的变化减小，从而提高了系统的实时性。

7. 发明授权

US09268542B1 Cache contention management on a multicore processor based on the degree of contention exceeding a threshold 有权
标题翻译：基于超过阈值的争用程度，在多核处理器上进行缓存争用管理
公开(公告)号：US09268542B1
公开(公告)日：2016-02-23
申请号：US13096821
申请日：2011-04-28
申请人： Jason Mars , Robert Hundt , Neil A. Vachharajani
发明人： Jason Mars , Robert Hundt , Neil A. Vachharajani
IPC分类号： G06F9/46 , G06F13/00 , G06F9/45 , G06F9/30 , G06F9/52 , G06F13/372 , G06F13/30
CPC分类号： G06F8/4442 , G06F9/30 , G06F9/46 , G06F9/5016 , G06F9/526 , G06F13/30 , G06F13/372 , G06F2209/504 , G06F2209/508 , Y02D10/22
摘要： A first indicator of a first number of cache misses to a cache memory of a multicore processor for a first application over a first time period is received. The first application executes on a first core of the processor and a second application simultaneously executes on a second core of the processor during the first time period. The first and second cores share the cache memory. A second indicator of a second number of cache misses to the cache memory for the first application over a second time period is received. During the second time period, the first application executes on the first core and the second application does not execute on the second core. A degree of contention among the first and second applications is determined based on the first and second indicators, and execution of the second application is adjusted based on the determined degree of contention.
摘要翻译：接收在第一时间段内针对第一应用的多核处理器的高速缓冲存储器的第一数量的高速缓存未命中的第一指示符。第一应用在处理器的第一核上执行，并且第二应用在第一时间段期间同时在处理器的第二核上执行。第一和第二核共享缓存。接收在第二时间段内针对第一应用的高速缓存存储器的第二数量的高速缓存未命中的第二指示符。在第二时间段期间，第一应用在第一核上执行，第二应用不在第二核上执行。基于第一和第二指示符确定第一和第二应用程序之间的争用程度，并且基于所确定的争用程度来调整第二应用的执行。

8. 发明申请

US20150356027A1 CIRCUITS FOR AND METHODS OF ENABLING THE ACCESS TO DATA 有权
标题翻译：电路访问数据的方法和方法
公开(公告)号：US20150356027A1
公开(公告)日：2015-12-10
申请号：US14301008
申请日：2014-06-10
申请人： Xilinx, Inc.
发明人： Ygal Arbel , James J. Murray , Hyun W. Kwon , Nishit Patel
IPC分类号： G06F12/14 , G06F13/30
CPC分类号： G06F12/145 , G06F13/00 , G06F13/28 , G06F13/30
摘要： A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.
摘要翻译：描述了一种能够访问数据的电路。该电路包括存储具有第一预定大小的数据块的存储器件; 以及直接存储器访问电路，其耦合到所述存储器件，所述直接存储器电路访问具有大于所述第一预定大小的第二预定尺寸的数据有效载荷; 其中所述直接存储器访问电路响应于具有对应于存储在所述存储器件中的预定数量的数据块的多个地址的描述符来访问所述数据有效载荷。还公开了一种能够访问数据的方法。

9. 发明申请

US20150347347A1 Dynamic Data Collection Communication Between Adapter Functions 有权
公开(公告)号：US20150347347A1
公开(公告)日：2015-12-03
申请号：US14826417
申请日：2015-08-14
申请人： International Business Machines Corporation
发明人： Omar Cardona , Baltazar De Leon, III , Marcus B. Grande , Brian W. Hart , Vikramjit Sethi
IPC分类号： G06F13/42 , G06F13/40 , G06F13/364
CPC分类号： G06F13/4282 , G06F13/30 , G06F13/364 , G06F13/385 , G06F13/404
摘要： An approach is provided that collects data from a multi-function adapter that is used by multiple functions. In the approach, a master function is dynamically selected from the group of functions. The approach further allows the master function to perform a disruptive adapter data collection while inhibiting performance of disruptive adapter data collection processes by the other (non-master) functions.

10. 发明授权

US09152590B2 Deterministic message processing in a direct memory access adapter 有权
公开(公告)号：US09152590B2
公开(公告)日：2015-10-06
申请号：US14277109
申请日：2014-05-14
申请人： International Business Machines Corporation
发明人： Michael A. Blocksome
IPC分类号： G06F13/30
CPC分类号： G06F13/30 , G06F13/28 , G06F2213/28
摘要： Deterministic message processing in a direct memory access (DMA) adapter includes the DMA adapter incrementing from a sub-head pointer, the sub-tail pointer until encountering an out-of-sequence packet. The DMA adapter also consumes packets between the sub-head pointer and the sub-tail pointer including incrementing with the consumption of each packet, the sub-head pointer until determining that the sub-head pointer is equal to the sub-tail pointer. In response to determining that the sub-head pointer is equal to the sub-tail pointer, the DMA adapter determines that the next in-sequence packet is not in the first FIFO message queue. In response to determining that the next in-sequence packet is not in the first FIFO message queue and that the first FIFO message queue exceeds a threshold capacity, the DMA controller copies the contents of the first FIFO message queue into the second FIFO message queue.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式