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1. 发明公开

US20240184723A1 METHOD AND SYSTEM FOR OBTAINING OPTIMAL NUMBER OF DMA CHANNELS 审中-公开
公开(公告)号：US20240184723A1
公开(公告)日：2024-06-06
申请号：US18216215
申请日：2023-06-29
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Hanju LEE
IPC分类号： G06F13/16 , G06F13/30
CPC分类号： G06F13/1673 , G06F13/30
摘要： The present disclosure provides methods and apparatuses for processing data. In some embodiments, the method includes operating a device by transmitting, to a host, first data using a plurality of direct memory access (DMA) channels regardless of an order of each DMA channel of the plurality of DMA channels. The method further includes obtaining an optimal number of the DMA channels based on a process capacity of a receiver buffer of the host. The method further includes transmitting, by the device to the host, second data based on the optimal number of the DMA channels.

2. 发明授权

US11983128B1 Multidimensional and multiblock tensorized direct memory access descriptors 有权
公开(公告)号：US11983128B1
公开(公告)日：2024-05-14
申请号：US18067109
申请日：2022-12-16
申请人： Amazon Technologies, Inc.
发明人： Kun Xu , Ron Diamant , Ilya Minkin , Mohammad El-Shabani , Raymond S. Whiteside , Uday Shilton Udayaselvam
IPC分类号： G06F13/30 , G06F13/16
CPC分类号： G06F13/30 , G06F13/1621 , G06F13/1642
摘要： Techniques to reduce overhead in a direct memory access (DMA) engine can include processing descriptors from a descriptor queue to obtain a striding configuration to generate tensorized memory descriptors. The striding configuration can include, for each striding dimension, a stride and a repetition number indicating a number of times to repeat striding in the corresponding striding dimension. One or more sets of tensorized memory descriptors can be generated based on the striding configuration. Data transfers are then performed based on the generated tensorized memory descriptors.

3. 发明公开

US20240143515A1 CACHING HOST MEMORY ADDRESS TRANSLATION DATA IN A MEMORY SUB-SYSTEM 审中-公开
公开(公告)号：US20240143515A1
公开(公告)日：2024-05-02
申请号：US18483790
申请日：2023-10-10
申请人： Micron Technology, Inc.
发明人： Sumangal Chakrabarty , Prateek Sharma , Raja V. S. Halaharivi , Yoav Weinberg , Di Hsien Ngu
IPC分类号： G06F12/1081 , G06F13/30
CPC分类号： G06F12/1081 , G06F13/30 , G06F2212/6022 , G06F2212/657
摘要： A system includes host interface circuitry to interact with a host system and that includes an address translation circuit, which includes request staging queues to buffer the address translation requests, each includes a virtual address and received from a host interface circuit. Pending response queues buffer respective address translation requests that are waiting for an address translation from the host system while maintaining an order as received within the request stage queues. Reordering buffers reorder address translations, which are to be supplied to the host interface circuits, according to the order maintained within the pending response queues, each address translation includes a physical address mapped to the virtual address of a corresponding address translation request. A cache stores multiple of the address translations, associated with the address translation requests, for future access by the host interface circuits.

4. 发明授权

US11954050B2 System and method for direct memory access 有权
公开(公告)号：US11954050B2
公开(公告)日：2024-04-09
申请号：US17301724
申请日：2021-04-13
申请人： NXP USA, Inc.
发明人： Jurgen Geerlings , Yang Liu , Zhijun Chen
IPC分类号： G06F13/00 , G06F12/02 , G06F12/0831 , G06F13/16 , G06F13/30
CPC分类号： G06F13/1668 , G06F12/0238 , G06F12/0835 , G06F13/1626 , G06F13/30
摘要： A method for direct memory access includes: receiving a direct memory access request designating addresses in a data block to be accessed in a memory; randomizing an order of the addresses the data block is accessed; and accessing the memory at addresses in the randomized order. A system for direct memory access is disclosed.

5. 发明申请

US20190196996A1 DYNAMICALLY DETERMINING MEMORY ACCESS BURST LENGTH 审中-公开
公开(公告)号：US20190196996A1
公开(公告)日：2019-06-27
申请号：US15851087
申请日：2017-12-21
申请人： Advanced Micro Devices, Inc.
发明人： Kedarnath Balakrishnan , Ravindra N. Bhargava , Guanhao Shen , James Raymond Magro , Kevin M. Brandl
IPC分类号： G06F13/30 , G06F13/16 , G06F3/06
CPC分类号： G06F13/30 , G06F3/061 , G06F3/0659 , G06F13/1642 , G06F13/1668
摘要： Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory read requests have been sent to a memory device in a read mode of a data bus, the memory controller determines a threshold number of memory write requests to send to the memory device in an upcoming write mode is a number of outstanding memory write requests. Alternatively, the memory controller determines the threshold number of memory write requests to send to the memory device in an upcoming write mode is a maximum value of the number of outstanding memory write requests and a programmable value of the write burst length stored in a control register. Therefore, the write burst length is determined dynamically. Similarly, the read burst length is determined dynamically when the write mode ends.

6. 发明授权

US09921985B2 Direct memory access controller 有权
公开(公告)号：US09921985B2
公开(公告)日：2018-03-20
申请号：US14860398
申请日：2015-09-21
申请人： Microchip Technology Incorporated
发明人： Joseph W. Triece , Rodney J. Pesavento , Gregg D. Lahti , Steven Dawson
IPC分类号： G06F13/28 , G06F13/00 , G06F13/34 , G06F13/30 , G06F13/16 , G06F13/40
CPC分类号： G06F13/34 , G06F13/1689 , G06F13/285 , G06F13/30 , G06F13/4022
摘要： A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

7. 发明申请

US20180052789A1 Direct Memory Access Transmission Control Method and Apparatus 审中-公开
公开(公告)号：US20180052789A1
公开(公告)日：2018-02-22
申请号：US15797605
申请日：2017-10-30
申请人： Huawei Technologies Co., Ltd.
发明人： Hao Chen , Huifeng Xu , Haitao Guo
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F7/74 , G06F7/76 , G06F7/78 , G06F9/5038 , G06F13/18 , G06F13/30 , G06F2213/2802
摘要： A direct memory access (DMA) transmission control method and apparatus, where the method includes selecting a target channel for the target DMA task according to a priority corresponding to the target DMA task when a DMA transmission request for transmitting data of a target DMA task is received, querying a task type and a priority of another DMA task that has occupied a channel and a task type of the target DMA task when the other DMA task exists on the DMA channel, comparing the task type and the priority of the other DMA task that has occupied the channel with the task type and the priority of the target DMA task, and controlling data transmission on the DMA channel according to a comparison result. Hence, the urgent DMA task can be preferentially processed.

8. 发明申请

US20170222790A1 CLOCK SUSTAIN IN THE ABSENCE OF A REFERENCE CLOCK IN A COMMUNICATION SYSTEM 审中-公开
公开(公告)号：US20170222790A1
公开(公告)日：2017-08-03
申请号：US15411801
申请日：2017-01-20
申请人： Analog Devices, Inc.
发明人： WILLIAM HOOPER , Lewis F. LAHR
IPC分类号： H04L7/00 , H04L7/02 , H04L12/40
CPC分类号： H04L7/0083 , G06F13/30 , G06F13/362 , H04H60/00 , H04J3/0647 , H04L7/04 , H04L12/40 , H04L12/403 , H04R5/00 , H04R2420/07 , H04R2460/03 , H04R2499/13
摘要： Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.

9. 发明授权

US09535826B2 Automatic communication and optimization of multi-dimensional arrays for many-core coprocessor using static compiler analysis 有权
标题翻译：使用静态编译器分析，为多核协处理器自动通信和优化多维数组
公开(公告)号：US09535826B2
公开(公告)日：2017-01-03
申请号：US14293667
申请日：2014-06-02
申请人： NEC Laboratories America, Inc.
发明人： Nishkam Ravi , Yi Yang , Srimat Chakradhar , Bin Ren
IPC分类号： G06F12/02 , G06F13/30 , G06F9/45 , G06F12/00
CPC分类号： G06F12/0207 , G06F8/41 , G06F8/443 , G06F8/51 , G06F12/023 , G06F13/30 , G06F2212/1016
摘要： There are provided source-to-source transformation methods for a multi-dimensional array and/or a multi-level pointer for a computer program. A method includes minimizing a number of holes for variable length elements for a given dimension of the array and/or pointer using at least two stride values included in stride buckets. The minimizing step includes modifying memory allocation sites, for the array and/or pointer, to allocate memory based on the stride values. The minimizing step further includes modifying a multi-dimensional memory access, for accessing the array and/or pointer, into a single dimensional memory access using the stride values. The minimizing step also includes inserting offload pragma for a data transfer of the array and/or pointer prior as at least one of a single-dimensional array and a single-level pointer. The data transfer is from a central processing unit to a coprocessor over peripheral component interconnect express.
摘要翻译：为计算机程序提供多维数组和/或多级指针的源到源转换方法。一种方法包括使用包括在步幅桶中的至少两个步幅值来最小化数组和/或指针的给定维度的可变长度元素的多个孔。最小化步骤包括修改针对阵列和/或指针的内存分配站点，以基于步幅值来分配存储器。最小化步骤还包括使用步幅值将用于访问阵列和/或指针的多维存储器访问修改为单维存储器访问。最小化步骤还包括在单维数组和单级指针中的至少一个之前插入用于数组和/或指针的数据传输的卸载pragma。数据传输是通过外围组件互连快递从中央处理单元到协处理器的。

10. 发明申请

US20160239443A1 DMA CONTROLLER 审中-公开
标题翻译： DMA控制器
公开(公告)号：US20160239443A1
公开(公告)日：2016-08-18
申请号：US15046389
申请日：2016-02-17
申请人： FANUC Corporation
发明人： Masahiro MIURA
IPC分类号： G06F13/30
CPC分类号： G06F13/30
摘要： A direct memory access (DMA) controller issues a standby request a predetermined period of time before data transfer having a high priority starts and prohibits data transfer having a low priority in advance, and thus data transfer having a high priority can generate a transfer cycle from a data transfer start point in time without waiting. Accordingly, a transfer time is reduced, a variation in the transfer time is reduced, and thus a real time property of a system is improved.
摘要翻译：直接存储器访问（DMA）控制器在具有高优先级的数据传输开始之前的预定时间段内发出待机请求，并且预先禁止具有低优先级的数据传输，因此具有高优先级的数据传输可以产生从数据传输起始点，无需等待。因此，传输时间减少，传输时间的变化减小，从而提高了系统的实时性。

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