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1. 发明授权

US07676527B2 Processor 有权
标题翻译：处理器
公开(公告)号：US07676527B2
公开(公告)日：2010-03-09
申请号：US10998012
申请日：2004-11-29
申请人： Shunichi Kuromaru , Koji Okamoto , Junji Michiyama
发明人： Shunichi Kuromaru , Koji Okamoto , Junji Michiyama
IPC分类号： G06F7/00
CPC分类号： G06F7/76
摘要： The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register. This arithmetic unit is suitable for being employed in an image processing system to perform the multiplexing processing or the demultiplexing processing for codes at high speeds.
摘要翻译：本发明提供了一种运算单元，包括用于存储外部输入的数字数据作为P位数字数据的输入寄存器，用于存储Q位数字数据的输出寄存器和输出位选择装置。输出位选择装置可用于接收从输入寄存器输出的P位数字数据作为第一输入数据，并将从输出寄存器输出的Q位数字数据作为第二输入数据。输出大选择装置还可用于根据从外部输入的控制数据，在第一输入数据的位和第二输入数据的位中选择要输出哪些位的位。输出位选择装置还可以用于将包括所选位的值的Q位数字数据输出到输出寄存器。该算术单元适合于在图像处理系统中使用以高速执行多路复用处理或多路分解处理。

2. 发明申请

US20080126906A1 Communication method and communication device 有权
标题翻译：通讯方式及通讯装置
公开(公告)号：US20080126906A1
公开(公告)日：2008-05-29
申请号：US11819290
申请日：2007-06-26
申请人： Tadanori Tezuka , Tsutomu Sekibe , Shunichi Kuromaru , Junji Michiyama , Hiroshi Nakamura , Masaaki Kondo , Takashi Nanya , Masashi Imai , Nassu Tomoyuki Bogdan
发明人： Tadanori Tezuka , Tsutomu Sekibe , Shunichi Kuromaru , Junji Michiyama , Hiroshi Nakamura , Masaaki Kondo , Takashi Nanya , Masashi Imai , Nassu Tomoyuki Bogdan
IPC分类号： G06F11/07 , H04L1/00
CPC分类号： H04L1/0025 , H04L51/063 , H04L67/32
摘要： A request change unit outputs a command as a request under control of a judgment control unit. A response condition determination unit determines a condition that is to be matched by a correct response which is to be returned from the other device-in-communication in reply to the command if the other device-in-communication operates in conformity with a protocol. A check unit checks a response received from the other device-in-communication in reply to the command, against the condition. If the received response does not match the condition but is correctable to match the condition as a result of the check, a response correction unit corrects the received response to match the condition under control of the judgment control unit.
摘要翻译：请求改变单元在判断控制单元的控制下输出作为请求的命令。响应条件确定单元如果其他设备在通信中的协议一致地操作，则确定要从其他设备在通信中返回的正确响应匹配的条件。检查单元根据该条件检查从其他通信设备接收的响应于该命令的响应。如果接收到的响应与条件不匹配，但是作为检查结果可以校正以匹配条件，则响应校正单元校正所接收的响应以与判断控制单元的控制下的条件相匹配。

3. 发明授权

US06791625B1 Video processing apparatus for performing address generation and control, and method therefor 失效
标题翻译：用于执行地址产生和控制的视频处理装置及其方法
公开(公告)号：US06791625B1
公开(公告)日：2004-09-14
申请号：US09868183
申请日：2001-07-12
申请人： Yasuo Kohashi , Toshihiro Moriiwa , Shunichi Kuromaru , Hiromasa Nakajima , Tomonori Yonezawa , Miki Arita
发明人： Yasuo Kohashi , Toshihiro Moriiwa , Shunichi Kuromaru , Hiromasa Nakajima , Tomonori Yonezawa , Miki Arita
IPC分类号： H04N964
CPC分类号： H04N19/43 , H04N19/423 , H04N19/51 , H04N19/61
摘要： Apparatus and method for data transmission while performing encoding processing on a non-limited moving vector mode, which avoids an increase in required memory capacity and a reduction in processing load, the apparatus comprising a two dimensional address generating unit for generating an access address of an external memory and an address control unit for administrating the horizontal position and the vertical position of the extended logical space and generating an operation authorizing signal for the two dimensional address generating unit, and the two dimensional address generating unit and the address control unit are operated in relation to each other so that an access address to outside the effective video data region is controlled to be an address of a pixel data at the periphery of the effective video data region, thereby reducing the extended region in the external memory.
摘要翻译：在对非限制的移动矢量模式进行编码处理时进行数据传输的装置和方法，其避免所需存储器容量的增加和处理负载的减少，所述装置包括二维地址生成单元，用于生成外部存储器和用于管理扩展逻辑空间的水平位置和垂直位置的地址控制单元，并且生成用于二维地址生成单元的操作授权信号，并且二维地址生成单元和地址控制单元在使得有效视频数据区域之外的访问地址被控制为有效视频数据区域的周边处的像素数据的地址，从而减少外部存储器中的扩展区域。

4. 发明授权

US06662288B1 Address generating apparatus and motion vector detector 有权
标题翻译：地址生成装置和运动矢量检测器
公开(公告)号：US06662288B1
公开(公告)日：2003-12-09
申请号：US09856775
申请日：2001-06-27
申请人： Mana Hamada , Shunichi Kuromaru , Tomonori Yonezawa
发明人： Mana Hamada , Shunichi Kuromaru , Tomonori Yonezawa
IPC分类号： G06F1208
CPC分类号： G06F3/0485 , G06F9/345 , G06F9/3455 , G06T7/238 , G06T2207/10016 , H04N19/433 , H04N19/51
摘要： A high-function address generating apparatus is realized which generates a memory address that can access a multidimensional area without running over a memory area specified by a user. Continuous addressing domain which is determined by a top address and a final address is set by an addressing domain setting means 101, an address is generated by a two-dimensional address generating means 106, the address in a two-dimensional area is compared with the final address and the top address by a first and a second comparing means 108 and 109, respectively, whether it runs over the addressing domain or not is judged by an address correction means 112, and an address running over is corrected so as to not run over.
摘要翻译：实现了高功能地址生成装置，其产生可以访问多维区域而不在用户指定的存储区域上运行的存储器地址。由寻址域设置装置101设置由顶部地址和最终地址确定的连续寻址域，由二维地址生成装置106产生地址，将二维区域中的地址与分别由第一和第二比较装置108和109分别确定地址是否通过寻址域运行的最终地址和顶部地址由地址校正装置112判断，并且运行的地址被校正以便不运行过度。

5. 发明授权

US07062633B1 Conditional vector arithmetic method and conditional vector arithmetic unit 失效
标题翻译：条件向量算法和条件向量运算单元
公开(公告)号：US07062633B1
公开(公告)日：2006-06-13
申请号：US09868048
申请日：1999-12-15
申请人： Mana Hamada , Shunichi Kuromaru , Tomonori Yonezawa , Tsuyoshi Nakamura
发明人： Mana Hamada , Shunichi Kuromaru , Tomonori Yonezawa , Tsuyoshi Nakamura
IPC分类号： G06F9/302 , G06F9/38
CPC分类号： G06F17/16
摘要： It is decided whether a first source data from the memory 101 is a data which is to be subjected to arithmetic or not by a state flag detection means 150, the result of the decision is retained as a state flag, and it is decided by a condition decision means 109 whether or not the state flag satisfies a condition for performing the arithmetic. A control means 110 controls whether an ALU 100 should perform the arithmetic or not on the basis of the condition satisfaction/dissatisfaction information.
摘要翻译：决定来自存储器101的第一源数据是否是由状态标志检测装置150进行算术的数据，判定结果被保留为状态标志，并且由条件判定单元109，判断状态标志是否满足进行运算的条件。控制装置110基于条件满足/不满意信息来控制ALU 100是否应该执行算术。

6. 发明申请

US20050108307A1 Arithmetic unit 有权
公开(公告)号：US20050108307A1
公开(公告)日：2005-05-19
申请号：US10998012
申请日：2004-11-29
申请人： Shunichi Kuromaru , Koji Okamoto , Junji Michiyama
发明人： Shunichi Kuromaru , Koji Okamoto , Junji Michiyama
IPC分类号： G06F7/76 , G06F7/00 , H04B14/04
CPC分类号： G06F7/76
摘要： The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register. This arithmetic unit is suitable for being employed in an image processing system to perform the multiplexing processing or the demultiplexing processing for codes at high speeds.

7. 发明授权

US06882688B1 Deblocking filter arithmetic apparatus and deblocking filter arithmetic method 失效
标题翻译：去块滤波算术装置和去块滤波算术方法
公开(公告)号：US06882688B1
公开(公告)日：2005-04-19
申请号：US09857779
申请日：1999-12-10
申请人： Masahiro Oohashi , Shunichi Kuromaru , Tsuyoshi Nakamura , Hiroki Ootsuki
发明人： Masahiro Oohashi , Shunichi Kuromaru , Tsuyoshi Nakamura , Hiroki Ootsuki
IPC分类号： H04N19/60 , H04N19/436 , H04N19/44 , H04N19/80 , H04N19/86 , H04N7/18
CPC分类号： H04N19/86 , H04N19/42 , H04N19/527 , H04N19/61
摘要： A deblocking filter arithmetic apparatus and a deblocking filter arithmetic method employed for removing block noises generated at decoding image data which have been subjected to the encoding process. Successive pixel data are input to eight arithmetic blocks (101˜108) every two data, a filtering processing arithmetic for removal of the block noises is carried out in parallel so as to conclude the filtering processing arithmetic in a unit of the combination of two arithmetic blocks in an order successively, thereby the pixel data obtained by performing the filtering processing are output by a pipeline system in a unit of the combination of the arithmetic blocks from an output selection circuit (8).
摘要翻译：一种去块滤波器运算装置和去块滤波器运算方法，用于去除在经过编码处理的图像数据解码时产生的块噪声。连续像素数据每两个数据被输入到八个算术块（101〜108），并行地执行用于去除块噪声的滤波处理算法，以便以两个算术的组合为单位来结束滤波处理算术按顺序依次排列，由输出选择电路（8）以运算块的组合为单位，由流水线系统输出通过进行滤波处理得到的像素数据。

8. 发明授权

US06671708B1 Processor and image processing device 有权
标题翻译：处理器和图像处理设备
公开(公告)号：US06671708B1
公开(公告)日：2003-12-30
申请号：US09600247
申请日：2000-08-31
申请人： Shunichi Kuromaru , Mana Hamada , Tomonori Yonezawa , Masatoshi Matsuo , Tsuyoshi Nakamura , Masahiro Oohashi
发明人： Shunichi Kuromaru , Mana Hamada , Tomonori Yonezawa , Masatoshi Matsuo , Tsuyoshi Nakamura , Masahiro Oohashi
IPC分类号： G06F738
CPC分类号： G06F9/3885 , G06F9/30036 , G06F17/10 , G06T1/20
摘要： An image processing apparatus according to the present invention comprises a general arithmetic circuit 101 comprising a program control circuit 103, a first address generator 104, a first data memory 105, a first pipeline operation circuit 106, a second address generator 113, a second data memory 114 and a second pipeline operation circuit 112, and a dedicated arithmetic circuit 102 comprising a control circuit 115, a first dedicated pipeline operation circuit 107, a second dedicated pipeline operation circuit 108, . . . , an N-th dedicated pipeline operation circuit 110, as shown in FIG. 1. The arithmetic unit having the above-described structure, for example, can realize an arithmetic unit which can be applied to various applications. Further, considering the age of IP (Intellectual Property) which will come in the future, the arithmetic unit can exhibit the flexibility toward the applications.
摘要翻译：根据本发明的图像处理装置包括通用运算电路101，其包括程序控制电路103，第一地址生成器104，第一数据存储器105，第一流水线运算电路106，第二地址发生器113，第二数据存储器114和第二流水线操作电路112，以及专用运算电路102，包括控制电路115，第一专用流水线运行电路107，第二专用流水线运行电路108。。。，第N专用流水线运算电路110，如图1所示。例如，具有上述结构的运算单元可以实现可应用于各种应用的算术单元。此外，考虑到将来会出现的知识产权（知识产权）的年龄，算术单位可以展现出应用的灵活性。

9. 发明授权

US07038737B1 Image processing device 失效
标题翻译：图像处理装置
公开(公告)号：US07038737B1
公开(公告)日：2006-05-02
申请号：US09856634
申请日：1999-11-25
申请人： Yasuo Kohashi , Toshihiro Moriiwa , Masayoshi Tojima , Shunichi Kuromaru , Masahiro Oohashi
发明人： Yasuo Kohashi , Toshihiro Moriiwa , Masayoshi Tojima , Shunichi Kuromaru , Masahiro Oohashi
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The image processing apparatus according to the present invention comprises: DMA control means 112 having image input/output processing means 100, an external memory 111, DMA setting holding means 113, address generating means 114, DRAM control means 115, DMA request generating means 119, and DMA request adjusting means 120; a processor 116 including encoding/decoding processing means 117; and a DMA bus 118 as shown in FIG. 1. In the image processing apparatus so constructed, a transfer data group which can be previously subjected to DMA scheduling is divided into burst transfer units, and the DMA request generating means periodically issues the DMA request in the burst transfer units and performs DMA of the transfer data which cannot be subjected to the DMA scheduling during the period that the DMA of the transfer data is not performed, thereby avoiding concentration of specific DMA.
摘要翻译：根据本发明的图像处理装置包括：具有图像输入/输出处理装置100，外部存储器111，DMA设置保持装置113，地址生成装置114，DRAM控制装置115，DMA请求生成装置119的DMA控制装置112 ，和DMA请求调整装置120; 包括编码/解码处理装置117的处理器116; 和DMA总线118，如图1所示。在这样构成的图像处理装置中，将可以预先进行DMA调度的传送数据组划分为突发传送单元，DMA请求生成单元在突发传送单元中周期性地发出DMA请求，并执行DMA 在不执行传输数据的DMA的时段内传送不能进行DMA调度的数据，从而避免特定DMA的集中。

10. 发明授权

US06901419B2 Arithmetic unit 有权
标题翻译：算术单位
公开(公告)号：US06901419B2
公开(公告)日：2005-05-31
申请号：US10366355
申请日：2003-02-14
申请人： Shunichi Kuromaru , Koji Okamoto , Junji Michiyama
发明人： Shunichi Kuromaru , Koji Okamoto , Junji Michiyama
IPC分类号： G06F7/76 , G06F7/00
CPC分类号： G06F7/76
摘要： The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register. This arithmetic unit is suitable for being employed in an image processing system to perform the multiplexing processing or the demultiplexing processing for codes at high speeds.
摘要翻译：本发明提供了一种运算单元，包括用于存储外部输入的数字数据作为P位数字数据的输入寄存器，用于存储Q位数字数据的输出寄存器和输出位选择装置。输出位选择装置可用于接收从输入寄存器输出的P位数字数据作为第一输入数据，并将从输出寄存器输出的Q位数字数据作为第二输入数据。输出大选择装置还可用于根据从外部输入的控制数据，在第一输入数据的位和第二输入数据的位中选择要输出哪些位的位。输出位选择装置还可以用于将包括所选位的值的Q位数字数据输出到输出寄存器。该算术单元适合于在图像处理系统中使用以高速执行多路复用处理或多路分解处理。

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