专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06503763B2 Method of making MFMOS capacitors with high dielectric constant materials 失效
标题翻译：制造高介电常数材料的MFMOS电容器的方法
公开(公告)号：US06503763B2
公开(公告)日：2003-01-07
申请号：US09819879
申请日：2001-03-27
申请人： Tingkai Li , Sheng Teng Hsu , Hong Ying , Bruce D. Ulrich , Yanjun Ma
发明人： Tingkai Li , Sheng Teng Hsu , Hong Ying , Bruce D. Ulrich , Yanjun Ma
IPC分类号： H01L2100
CPC分类号： H01L21/28291 , H01L29/516 , H01L29/78391
摘要： A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO2, HfO2, Y2O3, or La2O3, or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.
摘要翻译：用于铁电非易失性存储器件的MFMOS单晶体管存储器结构包括诸如ZrO 2，HfO 2，Y 2 O 3或La 2 O 3等的高介电常数材料或其混合物，以减少操作电压并增加存储窗口，设备的可靠性。

2. 发明授权

US06716645B2 MFMOS capacitors with high dielectric constant materials 有权
标题翻译：具有高介电常数材料的MFMOS电容器
公开(公告)号：US06716645B2
公开(公告)日：2004-04-06
申请号：US10319314
申请日：2002-12-12
申请人： Tingkai Li , Sheng Teng Hsu , Hong Ying , Bruce D. Ulrich , Yanjun Ma
发明人： Tingkai Li , Sheng Teng Hsu , Hong Ying , Bruce D. Ulrich , Yanjun Ma
IPC分类号： H01L2100
CPC分类号： H01L21/28291 , H01L29/516 , H01L29/78391
摘要： A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO2, HfO2, Y2O3, or La2O3, or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.
摘要翻译：用于铁电非易失性存储器件的MFMOS单晶体管存储器结构包括诸如ZrO 2，HfO 2，Y 2 O 3或La 2 O 3等的高介电常数材料或其混合物，以减少操作电压并增加存储窗口，设备的可靠性。

3. 发明授权

US06632731B2 Structure and method of making a sub-micron MOS transistor 失效
标题翻译：制造亚微米MOS晶体管的结构和方法
公开(公告)号：US06632731B2
公开(公告)日：2003-10-14
申请号：US09783760
申请日：2001-02-14
申请人： Yanjun Ma , David Russell Evans , Yoshi Ono , Sheng Teng Hsu
发明人： Yanjun Ma , David Russell Evans , Yoshi Ono , Sheng Teng Hsu
IPC分类号： H01L213205
CPC分类号： H01L29/6659 , H01L21/28088 , H01L21/28097 , H01L21/76895 , H01L21/76897 , H01L21/82385 , H01L29/42376 , H01L29/4966 , H01L29/4975 , H01L29/66545
摘要： A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.
摘要翻译：制造亚微米MOS晶体管的方法包括制备衬底，包括在其中分离有源区; 沉积栅氧化层; 在所述栅极氧化物层上沉积第一选择性可蚀刻层; 在第一选择性可蚀刻层上沉积第二选择性可蚀刻层; 蚀刻结构以切割第一选择性可蚀刻层; 在有源区中注入离子以形成源区和漏区; 沉积和平坦化氧化物; 去除剩余的第一选择性可蚀刻层和第二选择性可蚀刻层; 沉积栅电极; 并沉积氧化物并金属化该结构。亚微米MOS晶体管包括基板; 和有源区，包括具有小于1微米长度的栅区; 源区域，包括LDD源区域; 以及包括LDD漏极区域的漏极区域

4. 发明授权

US06573134B2 Dual metal gate CMOS devices and method for making the same 失效
公开(公告)号：US06573134B2
公开(公告)日：2003-06-03
申请号：US09817834
申请日：2001-03-27
申请人： Yanjun Ma , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Yanjun Ma , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L27/092
摘要： A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

5. 发明授权

US06441417B1 Single c-axis PGO thin film on ZrO2 for non-volatile memory applications and methods of making the same 失效
标题翻译：用于非易失性存储器应用的ZrO 2上的单个c轴PGO薄膜及其制造方法
公开(公告)号：US06441417B1
公开(公告)日：2002-08-27
申请号：US09820022
申请日：2001-03-28
申请人： Fengyan Zhang , Yanjun Ma , Jer-Shen Maa , Wei-Wei Zhuang , Sheng Teng Hsu
发明人： Fengyan Zhang , Yanjun Ma , Jer-Shen Maa , Wei-Wei Zhuang , Sheng Teng Hsu
IPC分类号： H01L2972
CPC分类号： H01L21/28291 , H01L21/31604 , H01L21/31691 , H01L28/56 , H01L29/516
摘要： A thin film structure includes a substantially single-phase, c-axis PGO film on an insulator for use in metal ferroelectric insulator semiconductor single transistor non-volatile memory applications. The PGO on insulator structure can also be used in capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. In a preferred embodiment, the PGO film is deposited on a Zirconium Oxide insulator layer.
摘要翻译：薄膜结构包括用于金属铁电绝缘体半导体单晶体管非易失性存储器应用的绝缘体上的基本单相c轴PGO膜。 PGO绝缘体结构也可用于电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件中。在优选实施例中，PGO膜沉积在氧化锆绝缘体层上。

6. 发明授权

US06403453B1 Dose control technique for plasma doping in ultra-shallow junction formations 有权
标题翻译：用于等离子体掺杂在超浅结结构中的剂量控制技术
公开(公告)号：US06403453B1
公开(公告)日：2002-06-11
申请号：US09626837
申请日：2000-07-27
申请人： Yoshi Ono , Yanjun Ma , Sheng Teng Hsu
发明人： Yoshi Ono , Yanjun Ma , Sheng Teng Hsu
IPC分类号： H01L2126
CPC分类号： H01L21/2236
摘要： A method of plasma doping substrates is provided. The substrate is covered with photoresist and placed within a plasma chamber. A doping gas is introduced into the chamber and ionized. A dilutant gas is also introduced to provide better control of the total amount of dosage associated with a given duration of exposure. The dilutant gas is preferably monatomic to reduce, or eliminate, affects associated with pressure variations within the chamber caused by dissociation of elements within the plasma chamber. The dilutant gas preferably contains lighter elements so as to reduce, or eliminate, damage to the photoresist caused by ion impacts. The dilutant gas is preferably neon or helium. The present method provides a means to better control the dosage and reduce photoresist damage and contamination.
摘要翻译：提供了一种等离子体掺杂衬底的方法。衬底被光致抗蚀剂覆盖并置于等离子体室内。将掺杂气体引入室并离子化。还引入稀释气体以更好地控制与给定的暴露持续时间相关的剂量的总量。稀释气体优选是单原子的，以减少或消除由等离子体室内的元素解离引起的室内压力变化的影响。稀释气体优选含有较轻的元素，以便减少或消除由离子冲击引起的光致抗蚀剂的损伤。稀释气体优选为氖气或氦气。本方法提供了更好地控制剂量并减少光致抗蚀剂损伤和污染的方法。

7. 发明授权

US06406947B1 Method of making a low leakage dynamic threshold voltage MOS (DTMOS) transistor 失效
标题翻译：制造低泄漏动态阈值电压MOS（DTMOS）晶体管的方法
公开(公告)号：US06406947B1
公开(公告)日：2002-06-18
申请号：US09740126
申请日：2000-12-18
申请人： Yanjun Ma , Sheng Teng Hsu
发明人： Yanjun Ma , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L29/66651 , H01L21/84 , H01L29/66772 , H01L29/783 , H01L29/7832 , H01L29/78612 , H01L29/78648
摘要： A method of fabricating a dynamic threshold voltage metal oxide semiconductor (DTMOS) for operation at threshold voltages less than 0.6 volts includes preparing a silicon substrate to form a trench in an active area; forming a silicon layer in the trench; doping the silicon layer in the trench to form a highly doped layer, having a doping ion concentration in a range of between about 5.0·1017 cm−3 and 5.0·1018 cm−3; depositing a silicon layer over the high doped silicon layer; and completing the structure to form a DTMOS transistor.
摘要翻译：制造用于在小于0.6伏特的阈值电压下操作的动态阈值电压金属氧化物半导体（DTMOS）的方法包括制备硅衬底以在有源区中形成沟槽; 在沟槽中形成硅层; 在沟槽中掺杂硅层以形成掺杂浓度在约5.0×10 17 cm -3至5.0×10 18 cm -3之间的掺杂离子浓度的高掺杂层; 在所述高掺杂硅层上沉积硅层; 并完成结构以形成DTMOS晶体管。

8. 发明授权

US06184157B2 Stress-loaded film and method for same 失效
标题翻译：应力负荷膜及其方法
公开(公告)号：US06184157B2
公开(公告)日：2001-02-06
申请号：US09088456
申请日：1998-06-01
申请人： Sheng Teng Hsu , Hongning Yang , David R. Evans , Tue Nguyen , Yanjun Ma
发明人： Sheng Teng Hsu , Hongning Yang , David R. Evans , Tue Nguyen , Yanjun Ma
IPC分类号： B05D306
CPC分类号： C23C14/50 , C23C14/06 , C23C14/22 , C23C16/30 , C23C16/44 , C23C16/4582
摘要： A method has been provided to counteract the inherent tension in a deposited film. A wafer substrate is fixed to a wafer chuck having a curved surface. When the chuck surface is convex, a tensile stress is implanted in a deposited film. Upon release from the chuck, the deposited film develops a compressive stress. When the chuck surface is concave, a compressive stress is implanted in the deposited film. Upon release from the chuck, the deposited film develops a tensile stress. Loading a film with a compressive stress is helpful in making films having an inherently tensile stress become thermal stable. Stress loading is also used to improve adhesion between films, and to prevent warping of a film during annealing. A product-by-process using the above-described method is also provided.
摘要翻译：已经提供了一种抵消沉积膜中的固有张力的方法。将晶片基板固定到具有弯曲表面的晶片卡盘。当卡盘表面凸出时，在沉积膜中注入拉伸应力。当从卡盘释放时，沉积的膜产生压缩应力。当卡盘表面凹陷时，在沉积膜中注入压应力。当从卡盘释放时，沉积的膜产生拉伸应力。加载具有压应力的薄膜有助于使具有固有拉伸应力的薄膜变得热稳定。应力负荷也用于提高膜之间的粘附性，并且防止退火期间膜的翘曲。还提供了使用上述方法的逐个方法。

9. 发明授权

US08759937B2 Schottky junction diode devices in CMOS with multiple wells 有权
标题翻译：具有多个阱的CMOS中的肖特基结二极管器件
公开(公告)号：US08759937B2
公开(公告)日：2014-06-24
申请号：US11387515
申请日：2006-03-22
申请人： Yanjun Ma , Ronald A. Oliver , Todd E. Humes , Jaideep Mavoori
发明人： Yanjun Ma , Ronald A. Oliver , Todd E. Humes , Jaideep Mavoori
IPC分类号： H01L27/095 , H01L29/872 , H01L29/66 , H01L27/06
CPC分类号： H01L29/872 , H01L27/0629 , H01L27/0814 , H01L29/66143
摘要： A Schottky junction diode device having improved performance and a multiple well structure is fabricated in a conventional CMOS process. A substrate including a material doped to a first conductivity type is formed. A first well is disposed over the substrate. The first well includes a material doped differently, such as to a second conductivity type opposite that of the first conductivity type. A second well is disposed within the first well. A region of metal-containing material is disposed in the second well to form a Schottky junction at an interface between the region of metal-containing material and the second well. In one embodiment, a second well contact is disposed in a portion of the second well.
摘要翻译：在传统的CMOS工艺中制造了具有改进的性能和多阱结构的肖特基结二极管器件。形成包括掺杂到第一导电类型的材料的衬底。第一阱设置在衬底上。第一阱包括不同掺杂的材料，例如与第一导电类型相反的第二导电类型。第二口井设置在第一井内。含金属材料的区域设置在第二阱中以在含金属材料区域和第二阱之间的界面处形成肖特基结。在一个实施例中，第二井接触设置在第二井的一部分中。

10. 发明授权

US07843032B1 Radio frequency identification device electrostatic discharge management 有权
标题翻译：射频识别装置静电放电管理
公开(公告)号：US07843032B1
公开(公告)日：2010-11-30
申请号：US11965307
申请日：2007-12-27
申请人： Cong Khieu , Yanjun Ma , Jaideep Mavoori
发明人： Cong Khieu , Yanjun Ma , Jaideep Mavoori
IPC分类号： H01L21/82
CPC分类号： H01L27/0251
摘要： Apparatus, systems, and methods may include managing electrostatic discharge events in radio frequency identification (RFID) devices by using a semiconductor circuit having a non-aligned gate to implement a snap-back voltage protection mechanism. Such circuits may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit including an RFID circuit that is supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed.
摘要翻译：装置，系统和方法可以包括通过使用具有非对准门的半导体电路来管理射频识别（RFID）装置中的静电放电事件来实现快速反向电压保护机制。这样的电路可以通过掺杂半导体衬底以形成第一导电区域而形成，以形成阱中的源极区域和漏极区域之一，在衬底上沉积多晶硅层以建立栅极区域与源极区域和漏极区域中的一个重叠，并且形成集成电路，该集成电路包括被衬底支撑以耦合到源区域和漏极区域中的一个的RFID电路，以在节点处提供快速恢复电压操作在集成电路和源极或漏极区之间。公开了附加装置，系统和方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式