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1. 发明申请

US20180286855A1 ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE AND METHOD FOR OPERATING AN ESD PROTECTION DEVICE 审中-公开
公开(公告)号：US20180286855A1
公开(公告)日：2018-10-04
申请号：US15471259
申请日：2017-03-28
申请人： NXP B.V.
发明人： Da-Wei Lai , Wei-Jhih Tseng
IPC分类号： H01L27/02 , H02H9/04
CPC分类号： H01L27/0277 , H01L27/0259 , H01L27/0262 , H01L27/0266 , H01L27/027 , H01L27/0292 , H01L29/0804 , H01L29/0821 , H01L29/0847 , H01L29/1004 , H01L29/1095 , H01L29/783 , H02H9/046
摘要： Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes stacked first and second PNP bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes and an NMOS transistor connected in series with the stacked first and second PNP bipolar transistors and the second node. An emitter and a base of the second PNP bipolar transistor are connected to a collector of the first PNP bipolar transistor. A gate terminal of the NMOS transistor is connected to a source terminal of the NMOS transistor. Other embodiments are also described.

2. 发明申请

US20180061976A1 INTEGRATED CIRCUIT STRUCTURE WITHOUT GATE CONTACT AND METHOD OF FORMING SAME 审中-公开
公开(公告)号：US20180061976A1
公开(公告)日：2018-03-01
申请号：US15797634
申请日：2017-10-30
申请人： GLOBALFOUNDRIES Inc.
发明人： Hui Zang , Manfred J. Eller , Min-Hwa Chi , Jerome J. B. Ciavatti
IPC分类号： H01L29/78 , H01L29/49 , H01L29/417 , H01L29/66
CPC分类号： H01L29/783 , H01L27/1104 , H01L29/41775 , H01L29/4975 , H01L29/66545 , H01L29/66795
摘要： One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

3. 发明授权

US09876015B1 Tight pitch inverter using vertical transistors 有权
公开(公告)号：US09876015B1
公开(公告)日：2018-01-23
申请号：US15434125
申请日：2017-02-16
申请人： International Business Machines Corporation
发明人： Karthik Balakrishnan , Kangguo Cheng , Pouya Hashemi , Alexander Reznicek
IPC分类号： H01L27/092 , H01L29/417 , H01L29/78 , H01L29/66 , H01L29/06 , H01L21/8238 , H01L23/528 , H01L27/082
CPC分类号： H01L27/092 , H01L21/823431 , H01L21/823487 , H01L21/823814 , H01L21/823821 , H01L21/823864 , H01L21/823871 , H01L21/823885 , H01L21/845 , H01L23/528 , H01L27/082 , H01L27/0924 , H01L27/11273 , H01L29/0649 , H01L29/41741 , H01L29/41791 , H01L29/66545 , H01L29/66666 , H01L29/66712 , H01L29/66795 , H01L29/7788 , H01L29/7802 , H01L29/7827 , H01L29/783 , H01L29/785 , H01L29/7853
摘要： CMOS inverters including gate-all-around vertical transistors are fabricated without requiring center gate contacts, thereby allowing close positioning of the transistors. The gate contact and the drain contact of the transistors are shared. Wiring of inverter input, output and power supply lines is simplified.

4. 发明授权

US09818842B2 Dynamic threshold MOS and methods of forming the same 有权
公开(公告)号：US09818842B2
公开(公告)日：2017-11-14
申请号：US15255731
申请日：2016-09-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jam-Wem Lee
IPC分类号： H01L21/336 , H01L29/66 , H01L27/088 , H01L29/06 , H01L21/762 , H01L27/06 , H01L27/12 , H01L29/78 , H01L21/304 , H01L21/324 , H01L21/768 , H01L29/786 , H01L23/48 , H01L21/18
CPC分类号： H01L29/66651 , H01L21/187 , H01L21/304 , H01L21/324 , H01L21/762 , H01L21/76224 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L27/0688 , H01L27/088 , H01L27/1203 , H01L29/0653 , H01L29/66477 , H01L29/78 , H01L29/783 , H01L29/78615 , H01L2224/11
摘要： A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. The DTMOS transistor includes a gate electrode, and a source/drain region adjacent to the gate electrode. The source/drain region is disposed in the well region. A well pickup region is in the well region, and the well pickup region is at a back side of the semiconductor substrate. The well pickup region is electrically connected to the gate electrode.

5. 发明授权

US09431289B2 Method and structure to reduce FET threshold voltage shift due to oxygen diffusion 有权
公开(公告)号：US09431289B2
公开(公告)日：2016-08-30
申请号：US14741618
申请日：2015-06-17
申请人： GLOBALFOUNDRIES INC.
发明人： Christopher V. Baiocco , Michael P. Chudzik , Deleep R. Nair , Jay M. Shah
IPC分类号： H01L21/76 , H01L21/762 , H01L29/66 , H01L29/06 , H01L29/78
CPC分类号： H01L21/76224 , H01L21/762 , H01L29/0649 , H01L29/66537 , H01L29/783
摘要： Oxygen scavenging material embedded in an isolation structure provides improved protection of high dielectric constant (Hi-K) materials from oxygen contamination while avoiding alteration of work function and switching threshold shift in transistors including such Hi-K materials.

6. 发明授权

US09136381B1 Super junction MOSFET with integrated channel diode 有权
标题翻译：具有集成通道二极管的超结MOSFET
公开(公告)号：US09136381B1
公开(公告)日：2015-09-15
申请号：US14546274
申请日：2014-11-18
申请人： Texas Instruments Incorporated
发明人： Christopher Boguslaw Kocon , John Manning Savidge Neilson , Simon John Molloy , Hideaki Kawahara
IPC分类号： H01L29/78 , H01L29/66 , H01L23/482
CPC分类号： H01L29/7832 , H01L23/4824 , H01L29/0634 , H01L29/0878 , H01L29/42376 , H01L29/66712 , H01L29/7802 , H01L29/7803 , H01L29/7805 , H01L29/783 , H01L2924/0002 , H01L2924/13091 , H01L2924/0001
摘要： Semiconductor device includes MOSFET having planar cells on an epitaxial semiconductor surface of a first type providing a drain drift region. A first and second epitaxial column formed in the semiconductor surface are doped a second type. A split gate includes planar gates between the epitaxial columns including a MOS gate electrode (MOS gate) and a diode gate electrode (diode gate). A body region of the second type in the drift region abuts the epitaxial columns. A source of the first type in the body region includes a first source portion proximate to the MOS gate and a second source portion proximate to the diode gate. A vertical drift region uses the drift region below the body region to provide a drain. A connector shorts the diode gate to the second source portion to provide an integrated channel diode. The MOS gate is electrically isolated from the first source portion.
摘要翻译：半导体器件包括在提供漏极漂移区的第一类型的外延半导体表面上具有平面单元的MOSFET。形成在半导体表面中的第一和第二外延柱掺杂第二类型。分离栅极包括在包括MOS栅极（MOS栅极）和二极管栅极（二极管栅极）的外延柱之间的平面栅极。漂移区域中第二类型的体区邻接外延柱。身体区域中的第一类型的源包括靠近MOS栅极的第一源极部分和靠近二极管栅极的第二源极部分。垂直漂移区域使用身体区域下方的漂移区域来提供排水。连接器将二极管栅极短路到第二源极部分以提供集成通道二极管。 MOS栅极与第一源极部分电气隔离。

7. 发明申请

US20150048443A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150048443A1
公开(公告)日：2015-02-19
申请号：US14513460
申请日：2014-10-14
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Fujio MASUOKA , Hiroki NAKAMURA
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L21/823885 , H01L27/092 , H01L29/0692 , H01L29/66666 , H01L29/7802 , H01L29/783
摘要： A semiconductor device includes a pillar-shaped silicon layer and a first-conductivity-type diffusion layer in an upper portion of the pillar-shaped silicon layer. A sidewall having a laminated structure including an insulating film and polysilicon resides on an upper sidewall of the pillar-shaped silicon layer. A top of the polysilicon of the sidewall is electrically connected to a top of the first-conductivity-type diffusion layer and has the same conductivity as the diffusion layer.
摘要翻译：半导体器件在柱状硅层的上部包括柱状硅层和第一导电型扩散层。具有绝缘膜和多晶硅层叠结构的侧壁位于柱状硅层的上侧壁上。侧壁的多晶硅的顶部电连接到第一导电型扩散层的顶部并且具有与扩散层相同的导电性。

8. 发明申请

US20140042505A1 DEVICE ACTIVE CHANNEL LENGTH/WIDTH GREATER THAN CHANNEL LENGTH/WIDTH 有权
标题翻译：器件有效通道长度/宽度大于通道长度/宽度
公开(公告)号：US20140042505A1
公开(公告)日：2014-02-13
申请号：US14112627
申请日：2011-05-19
申请人： Trudy Benjamín
发明人： Trudy Benjamín
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L27/0629 , B41J2/1433 , B41J2002/14491 , H01L21/823425 , H01L21/823456 , H01L21/823468 , H01L27/088 , H01L29/1033 , H01L29/66477 , H01L29/66568 , H01L29/78 , H01L29/783
摘要： A device including a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is situated over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.
摘要翻译：一种包括漏极，沟道和栅极的器件。通道围绕排水沟并具有通道长宽比。栅极位于通道上方，以提供有源通道区域，该有源沟道区域具有大于沟道长宽比的有源沟道区长宽比。

9. 发明申请

US20130307057A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130307057A1
公开(公告)日：2013-11-21
申请号：US13891584
申请日：2013-05-10
申请人： UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
发明人： Fujio MASUOKA , Hiroki NAKAMURA
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L21/823885 , H01L27/092 , H01L29/0692 , H01L29/66666 , H01L29/7802 , H01L29/783
摘要： A semiconductor device includes a first pillar-shaped silicon layer formed on a planar silicon layer, a gate insulating film formed around the first pillar-shaped silicon layer, a first gate electrode formed around the gate insulating film, a gate line connected to the first gate electrode, a first first-conductivity-type diffusion layer formed in an upper portion of the first pillar-shaped silicon layer, a second first-conductivity-type diffusion layer formed in a lower portion of the first pillar-shaped silicon layer and an upper portion of the planar silicon layer, a first sidewall having a laminated structure of an insulating film and polysilicon and being formed on an upper sidewall of the first pillar-shaped silicon layer and an upper portion of the first gate electrode, and a first contact formed on the first first-conductivity-type diffusion layer and the first sidewall.
摘要翻译：半导体器件包括形成在平坦硅层上的第一柱状硅层，围绕第一柱状硅层形成的栅极绝缘膜，形成在栅极绝缘膜周围的第一栅电极，与第一柱状硅层连接的栅极线栅电极，形成在第一柱状硅层的上部的第一第一导电型扩散层，形成在第一柱状硅层的下部的第二第一导电型扩散层和平面硅层的上部，具有绝缘膜和多晶硅层叠结构并形成在第一柱状硅层的上侧壁和第一栅电极的上部的第一侧壁，以及第一接触部形成在第一第一导电型扩散层和第一侧壁上。

10. 发明授权

US08482083B2 Semiconductor integrated circuit device including SRAM memory cells having two P-channel MOS transistors and four N-channel MOS transistors and with four wiring layers serving as their gate electrodes 有权
标题翻译：半导体集成电路器件包括具有两个P沟道MOS晶体管和四个N沟道MOS晶体管以及四个布线层作为其栅电极的SRAM存储单元
公开(公告)号：US08482083B2
公开(公告)日：2013-07-09
申请号：US12821329
申请日：2010-06-23
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L29/76 , H01L27/11
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.
摘要翻译：现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低导致出现微图案化困难的问题。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。在阵列的中间位置处，用于向衬底供电的区域形成为平行于字线，以这样的方式，每组三十二个存储单元行或六十六个单元行提供一个区域。

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