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1. 发明授权

US06275051B1 Segmented architecture for wafer test and burn-in 有权
标题翻译：用于晶圆测试和老化的分段架构
公开(公告)号：US06275051B1
公开(公告)日：2001-08-14
申请号：US09240121
申请日：1999-01-29
申请人： Thomas W. Bachelder , Dennis R. Barringer , Dennis R. Conti , James M. Crafts , David L. Gardell , Paul M. Gaschke , Mark R. Laforce , Charles H. Perry , Roger R. Schmidt , Joseph J. Van Horn , Wade H. White
发明人： Thomas W. Bachelder , Dennis R. Barringer , Dennis R. Conti , James M. Crafts , David L. Gardell , Paul M. Gaschke , Mark R. Laforce , Charles H. Perry , Roger R. Schmidt , Joseph J. Van Horn , Wade H. White
IPC分类号： G01R1073
CPC分类号： G01R31/2863
摘要： An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burning to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation. Evacuation also provides atmospheric pressure augmentation of contact for connection between boards and contact to wafer. Probes for parallel testing of chips are arranged in crescent shaped stripes to significantly increase tester throughput as compared with probes arranged in an area array.
摘要翻译：用于在产品晶片上同时测试或燃烧大量集成电路芯片的装置包括安装在第一板上的探针和安装在第二板上的测试器芯片，连接两个板的电连接器。测试器芯片用于向产品芯片分配电力或用于测试产品芯片。其所附接的探针和薄膜布线被个性化以用于被探测的特定晶片的焊盘覆盖区。第一板和第二板的基座对于产品系列中的所有晶片都保持不变。使用两个电路板提供了测试器芯片在燃烧期间保持在比产品芯片基本上更低的温度，以延长测试器芯片的寿命。间隙可以用作板之间的绝热，并将间隙密封并抽真空以进行进一步的隔热。疏散还提供大气压力增加的接触，用于连接板和与晶片的接触。用于平行测试芯片的探针被布置成月牙形条纹，以便与布置在区域阵列中的探针相比显着增加测试仪的吞吐量。

2. 发明授权

US06528145B1 Polymer and ceramic composite electronic substrates 有权
标题翻译：聚合物和陶瓷复合电子基板
公开(公告)号：US06528145B1
公开(公告)日：2003-03-04
申请号：US09606359
申请日：2000-06-29
申请人： Daniel George Berger , Shaji Farooq , Lester Wynn Herron , James N. Humenik , John Ulrich Knickerbocker , Robert William Pasco , Charles H. Perry , Krishna G. Sachdev
发明人： Daniel George Berger , Shaji Farooq , Lester Wynn Herron , James N. Humenik , John Ulrich Knickerbocker , Robert William Pasco , Charles H. Perry , Krishna G. Sachdev
IPC分类号： G02B600
CPC分类号： H05K1/0373 , H01L21/4857 , H01L23/49894 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0306 , H05K3/4611 , H05K2201/0129 , H05K2201/0141 , H05K2201/015 , H05K2201/0154 , H05K2201/0209 , H05K2201/0212 , H05K2201/068 , Y10S428/901 , Y10T428/24273 , Y10T428/24479 , Y10T428/24917 , Y10T428/24942 , Y10T428/249955 , Y10T428/249956 , Y10T428/251 , Y10T428/254 , Y10T428/259 , H01L2924/00
摘要： A composite electronic and/or optical substrate including polymeric and ceramic material wherein the composite substrate has a dielectric constant less than 4 and a coefficient of thermal expansion of 8 to 14 ppm/°C. at 100° C. The composite substrate may be either ceramic-filled polymeric material or polymer-filled ceramic material.
摘要翻译：包括聚合物和陶瓷材料的复合电子和/或光学基底，其中复合基底具有小于4的介电常数和8-14ppm /℃的热膨胀系数。在100℃下。复合衬底可以是陶瓷填充的聚合材料或聚合物填充的陶瓷材料。

3. 发明授权

US5277725A Process for fabricating a low dielectric composite substrate 失效
标题翻译：低介电复合衬底的制造方法
公开(公告)号：US5277725A
公开(公告)日：1994-01-11
申请号：US881448
申请日：1992-05-11
申请人： John Acocella , Peter A. Agostino , Arnold I. Baise , Richard A. Bates , Ray M. Bryant , Jon A. Casey , David R. Clarke , George Czornyj , Allen J. Dam , Lawrence D. David , Renuka S. Divakaruni , Werner E. Dunkel , Ajay P. Giri , Liang-Choo Hsia , James N. Humenik , Steven M. Kandetzke , Daniel P. Kirby , John U. Knickerbocker , Sarah H. Knickerbocker , Anthony Mastreani , Amy T. Matts , Robert W. Nufer , Charles H. Perry , Srinivasa S. N. Reddy , Salvatore J. Scilla , Mark A. Takacs , Lovell B. Wiggins
发明人： John Acocella , Peter A. Agostino , Arnold I. Baise , Richard A. Bates , Ray M. Bryant , Jon A. Casey , David R. Clarke , George Czornyj , Allen J. Dam , Lawrence D. David , Renuka S. Divakaruni , Werner E. Dunkel , Ajay P. Giri , Liang-Choo Hsia , James N. Humenik , Steven M. Kandetzke , Daniel P. Kirby , John U. Knickerbocker , Sarah H. Knickerbocker , Anthony Mastreani , Amy T. Matts , Robert W. Nufer , Charles H. Perry , Srinivasa S. N. Reddy , Salvatore J. Scilla , Mark A. Takacs , Lovell B. Wiggins
IPC分类号： H05K1/03 , C04B41/48 , C04B41/49 , H01L21/48 , H01L23/08 , H01L23/538 , H05K3/40 , C04B37/00 , B05D5/12
CPC分类号： H01L21/4857 , C04B41/488 , C04B41/4961 , H01L23/5383 , H05K3/4061 , C04B2111/00672 , C04B2111/00844 , H01L2924/0002 , H01L2924/09701 , H01L2924/12044 , H05K1/0306 , H05K2201/09581 , H05K2203/1147 , H05K2203/308
摘要： The cracking experienced during thermal cycling of metal:dielectric semiconductor packages results from a mismatch in thermal co-efficients of expansion. The non-hermeticity associated with such cracking can be addressed by backfilling the permeable cracks with a flexible material. Uniform gaps between the metal and dielectric materials can similarly be filled with flexible materials to provide stress relief, bulk compressibility and strength to the package. Furthermore, a permeable, skeletal dielectric can be fabricated as a fired, multilayer structure having sintered metallurgy and subsequently infused with a flexible, temperature-stable material to provide hermeticity and strength.
摘要翻译：在金属的热循环过程中经历的裂纹：电介质半导体封装是由热膨胀系数不匹配引起的。与这种开裂相关的非气密性可以通过用柔性材料回填可渗透裂缝来解决。金属和电介质材料之间的均匀间隙可以类似地填充柔性材料，以提供应力消除，体积可压缩性和包装的强度。此外，可渗透的骨架电介质可以被制造为具有烧结冶金的烧结多层结构，并随后注入柔性的温度稳定的材料以提供气密性和强度。

4. 发明授权

US06858111B2 Conductive polymer interconnection configurations 失效
标题翻译：导电聚合物互连配置
公开(公告)号：US06858111B2
公开(公告)日：2005-02-22
申请号：US09911069
申请日：2001-07-23
申请人： Charles H. Perry , Mark G. Courtney , Lewis S. Goldmann , Gregory B. Martin
发明人： Charles H. Perry , Mark G. Courtney , Lewis S. Goldmann , Gregory B. Martin
IPC分类号： H01L21/60 , H05K3/32 , H05K3/34 , C09J5/00
CPC分类号： H01L24/10 , B23K2101/36 , H01L24/13 , H01L24/29 , H01L24/83 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/05573 , H01L2224/13 , H01L2224/13099 , H01L2224/16225 , H01L2224/29101 , H01L2224/2919 , H01L2224/29339 , H01L2224/29344 , H01L2224/29364 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/09701 , H01L2924/14 , H05K3/321 , H05K3/3436 , H05K2201/0129 , H05K2201/10674 , H05K2201/10734 , H05K2201/10992 , Y02P70/613 , Y10T428/256 , Y10T428/26 , Y10T428/31678 , H01L2924/00 , H01L2924/00014 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929
摘要： A method of forming an electrical connection between two devices is disclosed. In an exemplary embodiment of the invention, the method includes soldering a second solderable cap of an interconnection to a first contact pad of a first component. The interconnection further includes a conductive polymer comprising a polymer component and a conductive component A first solderable cap is disposed in contact with the conductive polymer, and the second solderable cap is disposed in contact with the conductive polymer opposite the first solderable cap. The first solderable cap is then soldered to a second contact pad of a second component.
摘要翻译：公开了一种在两个装置之间形成电连接的方法。在本发明的示例性实施例中，该方法包括将互连的第二可焊接焊锡焊接到第一部件的第一接触焊盘。互连还包括包含聚合物组分和导电组分的导电聚合物。第一可焊接帽设置成与导电聚合物接触，并且第二可焊接帽设置成与第一可焊接帽相对的导电聚合物接触。然后将第一可焊接帽焊接到第二部件的第二接触焊盘。

5. 发明授权

US06848914B2 Electrical coupling of substrates by conductive buttons 有权
标题翻译：通过导电按钮电连接基板
公开(公告)号：US06848914B2
公开(公告)日：2005-02-01
申请号：US09975213
申请日：2001-10-11
申请人： Brian S. Beaman , William L. Brodsky , James A. Busby , Benson Chan , Voya R. Markovich , Charles H. Perry
发明人： Brian S. Beaman , William L. Brodsky , James A. Busby , Benson Chan , Voya R. Markovich , Charles H. Perry
IPC分类号： H01R12/52 , H01R13/24 , H01R43/00 , H01R12/00
CPC分类号： H01R43/007 , H01R12/52 , H01R13/2421
摘要： A structure and method for electrically coupling two substrates (e.g., a printed wiring board and an electronic module). Initially, a dielectric core is provided. A conductive wiring is helically wound circumferentially around the dielectric core. Additionally, a dielectric jacket may be formed around the conductive wiring. The resultant conductive rod structure is cut axially along the length of the conductive rod to generate conductive buttons having end contacts. The end contacts of the conductive buttons may be used to electrically couple the two substrates at corresponding pads of the two substrates.
摘要翻译：用于电耦合两个基板（例如，印刷线路板和电子模块）的结构和方法。首先，提供介质芯。导电布线围绕介质芯螺旋缠绕。此外，可以在导电布线周围形成电介质护套。所得的导电杆结构沿着导电棒的长度被轴向地切割，以产生具有端部触头的导电按钮。导电按钮的端部触点可用于将两个基板电耦合到两个基板的相应焊盘处。

6. 发明授权

US06333104B1 Conductive polymer interconnection configurations 失效
标题翻译：导电聚合物互连配置
公开(公告)号：US06333104B1
公开(公告)日：2001-12-25
申请号：US09580131
申请日：2000-05-30
申请人： Charles H. Perry , Mark G. Courtney , Lewis s. Goldmann , Gregory B. Martin
发明人： Charles H. Perry , Mark G. Courtney , Lewis s. Goldmann , Gregory B. Martin
IPC分类号： B32B516
CPC分类号： H01L24/10 , B23K2101/36 , H01L24/13 , H01L24/29 , H01L24/83 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/05573 , H01L2224/13 , H01L2224/13099 , H01L2224/16225 , H01L2224/29101 , H01L2224/2919 , H01L2224/29339 , H01L2224/29344 , H01L2224/29364 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/09701 , H01L2924/14 , H05K3/321 , H05K3/3436 , H05K2201/0129 , H05K2201/10674 , H05K2201/10734 , H05K2201/10992 , Y02P70/613 , Y10T428/256 , Y10T428/26 , Y10T428/31678 , H01L2924/00 , H01L2924/00014 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929
摘要： Disclosed herein is an interconnection for electrical connection of two electrical devices. The interconnection comprises a conductive polymer disposed in contact with one or two solderable caps. Together, the solderable cap(s) and the conductive polymer form an interconnection that can be used to connect two electrical devices through the contact pads on the electrical devices. For example, a packaged integrated circuit chip can be connected to a “card” using an array of the interconnections. Since the interconnection has solderable surfaces, the interconnect can be used in place of solder balls in a conventional manufacturing line.
摘要翻译：这里公开了用于两个电气设备的电连接的互连。互连包括与一个或两个可焊接盖接触设置的导电聚合物。一起，可焊接帽和导电聚合物形成互连，其可以用于通过电气设备上的接触焊盘连接两个电气设备。例如，封装的集成电路芯片可以使用互连阵列连接到“卡”。由于互连具有可焊接表面，所以可以使用互连来代替常规生产线中的焊球。

7. 发明授权

US5135595A Process for fabricating a low dielectric composite substrate 失效
标题翻译：制造低介电复合基板的工艺
公开(公告)号：US5135595A
公开(公告)日：1992-08-04
申请号：US503495
申请日：1990-03-30
申请人： John Acocella , Peter A. Agostino , Arnold I. Baise , Richard A. Bates , Ray M. Bryant , Jon A. Casey , David R. Clarke , George Czornyj , Allen J. Dam , Lawrence D. David , Renuka S. Divakaruni , Werner E. Dunkel , Ajay P. Giri , Liang-Choo Hsia , James N. Humenik , Steven M. Kandetzke , Daniel P. Kirby , John U. Knickerbocker , Sarah H. Knickerbocker , Anthony Mastreani , Amy T. Matts , Robert W. Nufer , Charles H. Perry , Srinivasa S. N. Reddy , Salvatore J. Scilla , Mark A. Takacs , Lovell B. Wiggins
发明人： John Acocella , Peter A. Agostino , Arnold I. Baise , Richard A. Bates , Ray M. Bryant , Jon A. Casey , David R. Clarke , George Czornyj , Allen J. Dam , Lawrence D. David , Renuka S. Divakaruni , Werner E. Dunkel , Ajay P. Giri , Liang-Choo Hsia , James N. Humenik , Steven M. Kandetzke , Daniel P. Kirby , John U. Knickerbocker , Sarah H. Knickerbocker , Anthony Mastreani , Amy T. Matts , Robert W. Nufer , Charles H. Perry , Srinivasa S. N. Reddy , Salvatore J. Scilla , Mark A. Takacs , Lovell B. Wiggins
IPC分类号： H05K1/03 , C04B41/48 , C04B41/49 , H01L21/48 , H01L23/08 , H01L23/538 , H05K3/40
CPC分类号： H01L21/4857 , C04B41/488 , C04B41/4961 , H01L23/5383 , H05K3/4061 , C04B2111/00672 , C04B2111/00844 , H01L2924/0002 , H01L2924/09701 , H01L2924/12044 , H05K1/0306 , H05K2201/09581 , H05K2203/1147 , H05K2203/308
摘要： The cracking experienced during thermal cycling of metal:dielectric semiconductor packages results from a mismatch in thermal co-efficients of expansion. The non-hermeticity associated with such cracking can be addresssed by backfilling the permeable cracks with a flexible material. Uniform gaps between the metal and dielectric materials can similarly be filled with flexible materials to provide stress relief, bulk compressibility and strength to the package. Furthermore, a permeable, skeletal dielectric can be fabricated as a fired, multilayer structure having sintered metallurgy and subsequently infused with a flexible, temperature-stable material to provide hermeticity and strength.

8. 发明授权

US07278207B2 Method of making an electronic package 失效
公开(公告)号：US07278207B2
公开(公告)日：2007-10-09
申请号：US11182167
申请日：2005-07-15
申请人： Lisa J. Jimarez , Miguel A. Jimarez , Voya R. Markovich , Cynthia S. Milkovich , Charles H. Perry , Brenda L. Peterson
发明人： Lisa J. Jimarez , Miguel A. Jimarez , Voya R. Markovich , Cynthia S. Milkovich , Charles H. Perry , Brenda L. Peterson
IPC分类号： H01K3/10 , H01R12/04 , H01L21/00
CPC分类号： H01L21/4857 , H01L21/486 , H01L23/15 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L2924/0002 , H05K1/0271 , H05K1/0306 , H05K1/113 , H05K3/3436 , H05K3/3457 , H05K3/4053 , H05K3/4069 , H05K3/4605 , H05K3/4644 , H05K3/4688 , H05K2201/0133 , H05K2201/015 , H05K2201/09436 , H05K2201/09509 , H05K2201/10734 , H05K2203/061 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49153 , Y10T29/49165 , H01L2924/00
摘要： An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.

9. 发明授权

US06486415B2 Compliant layer for encapsulated columns 有权
标题翻译：封装柱的合规层
公开(公告)号：US06486415B2
公开(公告)日：2002-11-26
申请号：US09761124
申请日：2001-01-16
申请人： Lisa J. Jimarez , Miguel A. Jimarez , Voya R. Markovich , Cynthia S. Milkovich , Charles H. Perry , Brenda L. Peterson
发明人： Lisa J. Jimarez , Miguel A. Jimarez , Voya R. Markovich , Cynthia S. Milkovich , Charles H. Perry , Brenda L. Peterson
IPC分类号： H01P1204
CPC分类号： H01L21/4857 , H01L21/486 , H01L23/15 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L2924/0002 , H05K1/0271 , H05K1/0306 , H05K1/113 , H05K3/3436 , H05K3/3457 , H05K3/4053 , H05K3/4069 , H05K3/4605 , H05K3/4644 , H05K3/4688 , H05K2201/0133 , H05K2201/015 , H05K2201/09436 , H05K2201/09509 , H05K2201/10734 , H05K2203/061 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49153 , Y10T29/49165 , H01L2924/00
摘要： An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.
摘要翻译：提供电子封装和制造电子封装的方法。电介质材料层位于包括多个导电触点的衬底的第一表面上。至少一个通孔形成在电介质材料层中，与多个导电触点中的至少一个对准。导电材料位于基本上填充通孔的至少一个通孔中。至少一个导电构件定位在通孔中的导电材料上并与导电材料电接触。该电子封装提高了组件的现场使用寿命，该组件包括附接到衬底的第二表面的半导体芯片和附着到导电构件的印刷线路板。

10. 发明授权

US6038931A Method and apparatus for the testing of plastically deformable objects 失效
标题翻译：用于测试塑性变形物体的方法和装置
公开(公告)号：US6038931A
公开(公告)日：2000-03-21
申请号：US25672
申请日：1998-02-18
申请人： David C. Long , Thomas P. Moyer , Keith C. O'Neil , Charles H. Perry , Glenn A. Pomerantz , James R. Case , Laszlo Kando , John E. Kozol
发明人： David C. Long , Thomas P. Moyer , Keith C. O'Neil , Charles H. Perry , Glenn A. Pomerantz , James R. Case , Laszlo Kando , John E. Kozol
IPC分类号： G01N3/24 , G01N3/20
CPC分类号： G01N3/24
摘要： A method for testing the integrity at least two test objects, each object is made of a plastically deformable material, by a. contacting a moving means with the objects at a first point in time, the moving means at a first position and the objects at a first position, the moving means having a shaped portion; b. shifting at least a portion of the objects to a second position at a second time, subsequent to the first time, wherein at least a portion of the objects were displaced during the interval between the first time and the second time; c. evaluating the objects after the shifting in step b. 22.
摘要翻译：一种用于测试至少两个测试对象的完整性的方法，每个对象由可塑性变形的材料制成，由a。在第一时间点将移动装置与物体接触，移动装置处于第一位置，并且物体处于第一位置，移动装置具有成形部分; b。在第一次之后的第二时间将至少一部分物体移动到第二位置，其中至少一部分物体在第一时间和第二时间之间的间隔期间被移位; C。在步骤b中移动后评估对象。 22。

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