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1. 发明授权

US5959995A Asynchronous packet switching 失效
标题翻译：异步分组交换
公开(公告)号：US5959995A
公开(公告)日：1999-09-28
申请号：US605677
申请日：1996-02-22
申请人： Thomas M. Wicki , Patrick J. Helland , Takeshi Shimizu , Wolf-Dietrich Weber , Winfried W. Wilcke
发明人： Thomas M. Wicki , Patrick J. Helland , Takeshi Shimizu , Wolf-Dietrich Weber , Winfried W. Wilcke
IPC分类号： G06F15/17 , H04L12/56 , H04J3/24
CPC分类号： H04L45/00 , H04L45/34
摘要： A multiprocessor system includes a plurality of nodes and an interconnect that includes routers. Each node includes a reliable packet mover and a fast frame mover. The reliable packet mover provides packets to the fast frame mover which adds routing information to the packet to form a frame. The route to each node is predetermined. The frame is provided to the routers which delete the route from the routing information. If the frame is lost while being routed, the router discards the frame. If the packet is received at a destination node, the reliable packet mover in that node sends an acknowledgment to the source node if the packet passes an error detection test. The reliable packet mover in the source node resends the packet if it does not receive an acknowledgment in a predetermined time. The fast frame mover randomly selects the route from a plurality of predetermined routes to the destination node according to a probability distribution.
摘要翻译：多处理器系统包括多个节点和包括路由器的互连。每个节点包括可靠的分组移动器和快速帧移动器。可靠的分组移动器向快速帧移动器提供分组，其将路由信息添加到分组以形成帧。到每个节点的路由是预定的。该帧被提供给从路由信息中删除路由的路由器。如果在路由时帧丢失，路由器将丢弃帧。如果在目的地节点处接收到分组，则如果分组通过错误检测测试，则该节点中的可靠分组移动器向源节点发送确认。如果源节点中的可靠的分组移动器在预定时间内没有接收到确认，则重新发送分组。快速帧移动器根据概率分布从多个预定路由到目的地节点随机选择路由。

2. 发明授权

US06393023B1 System and method for acknowledging receipt of messages within a packet based communication network 失效
标题翻译：用于确认在基于分组的通信网络内的消息的接收的系统和方法
公开(公告)号：US06393023B1
公开(公告)日：2002-05-21
申请号：US09075461
申请日：1998-05-08
申请人： Takeshi Shimizu , Wolf-Dietrich Weber , Patrick J. Helland , Thomas M. Wicki , Winfried W. Wilcke
发明人： Takeshi Shimizu , Wolf-Dietrich Weber , Patrick J. Helland , Thomas M. Wicki , Winfried W. Wilcke
IPC分类号： H04L1256
CPC分类号： H04L1/1867 , H04L1/16 , H04L1/1874 , H04L1/188
摘要： A system and method for acknowledging receipt of messages within a packet based communication network. A sending node generates a data packet within an upper layer, and transmits the data packet to a receiving node using a lower layer. The lower layer generates and transmits a pseudo reply packet to the upper layer in response to an acknowledgment received from the receiving node. The pseudo reply packet notifies the upper layer of the sending node that the receiving node successfully received the data packet and removes the burden of having an upper layer of the receiving node generate an actual reply packet.
摘要翻译：一种用于在基于分组的通信网络内确认接收到消息的系统和方法。发送节点在上层生成数据包，并使用较低层将数据包发送到接收节点。响应于从接收节点接收的确认，下层生成并向上层发送伪应答分组。伪应答分组通知发送节点的上层接收节点成功接收到数据分组，并消除了接收节点的上层生成实际应答分组的负担。

3. 发明授权

US5740346A System and method for dynamic network topology exploration 失效
标题翻译：动态网络拓扑探索的系统与方法
公开(公告)号：US5740346A
公开(公告)日：1998-04-14
申请号：US605676
申请日：1996-02-22
申请人： Thomas M. Wicki , Patrick J. Helland , Wolf-Dietrich Weber , Winfried W. Wilcke
发明人： Thomas M. Wicki , Patrick J. Helland , Wolf-Dietrich Weber , Winfried W. Wilcke
IPC分类号： H04L12/56
CPC分类号： H04L45/02
摘要： A system and method dynamically determines the topology of a source node routing network while having a minimal effect on network performance and without requiring expensive hardware to implement. A source node generates a ping frame. The source node transmits the ping frame to a first source router that is coupled to the source node. The first router transparently identifies the frame as a ping frame and creates an echo frame that is transmitted back to the source node. The first router identifies the port from which the ping frame is received and places this information in the header of the echo frame along with an echo frame identifier. The source node receives the echo frame and identifies routers and nodes to which a ping frame has not been sent based upon the connectivity information in the received echo frame. The source node continue generating and transmitting ping frame to all nodes and routers in the network. The source node identifies loops in the topology to avoid repetitive checking and identifies link and router failures. The topology exploration technique is transparent to the routers The topology exploration techique can be implemented during slow traffic periods with no increase in network latency or the technique can be implemented during high traffic periods and result in only a minimal increase in system latency because ping frames are small and are transparently sent to the control frame handler of the destination router or node.
摘要翻译：系统和方法动态地确定源节点路由网络的拓扑，同时对网络性能影响最小，而不需要昂贵的硬件来实现。源节点生成ping帧。源节点将ping帧发送到耦合到源节点的第一源路由器。第一个路由器将该帧透明地识别为一个ping帧，并创建一个发送回源节点的回波帧。第一个路由器识别从其接收ping帧的端口，并将该信息与回波帧标识符一起放置在回波帧的报头中。根据所接收的回波帧中的连通性信息，源节点接收回波帧并识别尚未发送ping帧的路由器和节点。源节点继续生成并发送Ping帧到网络中的所有节点和路由器。源节点标识拓扑中的循环，以避免重复检查，并识别链路和路由器故障。拓扑探索技术对于路由器是透明的。拓扑探索技术可以在较慢的流量周期内实现，而不会增加网络延迟，或者在高流量时段内可以实现该技术，并且只能使系统延迟最小化，因为ping帧并且被透明地发送到目的地路由器或节点的控制帧处理器。

4. 发明授权

US06003064A System and method for controlling data transmission between network elements 失效
标题翻译：控制网元之间数据传输的系统和方法
公开(公告)号：US06003064A
公开(公告)日：1999-12-14
申请号：US603913
申请日：1996-02-22
申请人： Thomas M. Wicki , Patrick J. Helland , Jeffrey D. Larson , Albert Mu , Raghu Sastry , Richard L. Schober, Jr.
发明人： Thomas M. Wicki , Patrick J. Helland , Jeffrey D. Larson , Albert Mu , Raghu Sastry , Richard L. Schober, Jr.
IPC分类号： H04L29/08 , H04L12/56 , H04L13/08 , G06F13/12 , G06F13/14
CPC分类号： H04L47/30 , H04L47/10 , H04L47/26
摘要： A system and method for controlling data transmission between two network elements. A first port of a transmitting element is coupled to a second port of a receiving element. The second port includes buffers for temporarily storing received data until the data can be sent to another element. Included in the transmitting element are a received-currently-full register (RCFR), a sent-and-not-received register (SANRR), and a buffer-busy register (BBR). The transmitting element checks its BBR to determine if a buffer in the receiving element is available. The availability of buffers can be determined using a single priority protocol or a multiple priority protocol. If a buffer is available, the transmitting element transmits a data frame to the receiving element and sets the SANRR and the BBR to indicate that a frame has been sent (and that no acknowledgment has been received), that the selected buffer in the receiver is full, and that no additional data frames are to be sent to this buffer until the buffer is empty. When data is received by the receiving element, it is sent to an available buffer. When the data is received by the buffer, the receiving element sets a bit in a currently-full register (CFR) and a bit in a next-message-to-send register (NMTSR). A control signal is transmitted by the data receiving element on the same signal line as data that is being sent from the data receiving element to the data transmitting element. The data receiving element can multiplex the frames being sent in this direction with the control signal. When the transmitting element receives the control signal, it resets a bit associated with a buffer in the SANRR if the bit is set in the SANRR and if the associated bit in the NMTSR portion of the control signal is set.
摘要翻译：一种用于控制两个网络元件之间的数据传输的系统和方法。发射元件的第一端口耦合到接收元件的第二端口。第二端口包括用于临时存储接收到的数据的缓冲器，直到可以将数据发送到另一个元件。包含在发送元件中的是接收当前完整寄存器（RCFR），发送 - 未接收寄存器（SANRR）和缓冲器 - 忙寄存器（BBR）。发送元件检查其BBR以确定接收元件中的缓冲区是否可用。可以使用单一优先级协议或多优先级协议来确定缓冲区的可用性。如果缓冲器可用，则发送元件向接收元件发送数据帧，并将SANRR和BBR设置为指示已经发送了帧（并且没有接收到确认），接收器中所选择的缓冲器是完全，并且在缓冲区为空之前，不会将其他数据帧发送到此缓冲区。当接收元件接收到数据时，它被发送到可用的缓冲器。当数据被缓冲器接收时，接收单元设置当前完整寄存器（CFR）中的位和下一个消息发送寄存器（NMTSR）中的位。控制信号由数据接收元件在与数据接收元件发送到数据发送元件的数据相同的信号线上发送。数据接收元件可以将在该方向上发送的帧与控制信号进行复用。当发送元件接收到控制信号时，如果在SANRR中设置该位，并且控制信号的NMTSR部分中的关联位被置位，则复位与SANRR中的缓冲器有关的位。

5. 发明授权

US5768300A Interconnect fault detection and localization method and apparatus 失效
公开(公告)号：US5768300A
公开(公告)日：1998-06-16
申请号：US603911
申请日：1996-02-22
申请人： Raghu Sastry , Jeffrey D. Larson , Albert Mu , John R. Slice , Richard L. Schober, Jr. , Thomas M. Wicki
发明人： Raghu Sastry , Jeffrey D. Larson , Albert Mu , John R. Slice , Richard L. Schober, Jr. , Thomas M. Wicki
IPC分类号： H04L1/00 , H04L1/08 , H04L1/24 , H04L12/26 , G06F11/10 , H03M13/00
CPC分类号： H04L1/0057 , H04L1/08 , H04L1/24 , H04L12/2697 , H04L43/50
摘要： A method and apparatus for detecting and isolating an interconnect fault in a packet switched network generates a parity check error code for status messages which are used for flow control in a packet switched network. The packet switched network uses a reverse flow control method wherein status messages are sent locally between adjacent nodes. A receiving node uses status messages to inform an adjacent node of the availability of the input buffers located in the receiving node. Included in the status message is a parity check code that is sent sequentially with the status message using two phases of a clock. The parity check code is a one bit parity check for each bit of the status message. Faults on the local interconnect are detected at the receiving node by performing a one bit parity check on the received status message using the accompanying parity code. Because the status message and the parity check code are transmitted over the same physical bit connections, the one bit parity checks detects any "stuck at" or "open" faults in the link.

6. 发明授权

US07523342B1 Data and control integrity for transactions in a computer system 有权
标题翻译：计算机系统中事务的数据和控制完整性
公开(公告)号：US07523342B1
公开(公告)日：2009-04-21
申请号：US11262254
申请日：2005-10-28
申请人： Peter L. Fu , Thomas M. Wicki
发明人： Peter L. Fu , Thomas M. Wicki
IPC分类号： G06F11/08 , G06F11/10
CPC分类号： H04L1/0045
摘要： A computer system configured to enhance data protection. A computer system includes one or more clients, such as processing subsystems and a memory subsystem interconnected via a network. Transactions within the system may involve the separation of data and a corresponding address in both space and time. At various points in the system, operations may be performed which seek to reunite a data and corresponding address, such as a store operation. In order to further ensure the correspondence of data and an address which is to be used in an operation, clients are configured to generate and utilize an additional symbol. The symbol is generated at least in part on an address which corresponds to data. The symbol is then associated with the data and serves to represent the corresponding address. The symbol may then be utilized by various clients within the system to check an address which is proposed to be used in an operation with the data.
摘要翻译：配置为增强数据保护的计算机系统。计算机系统包括一个或多个客户端，诸如处理子系统和经由网络互连的存储器子系统。系统内的事务可能涉及在空间和时间上分离数据和相应的地址。在系统的各个点处，可以执行寻求重新统一数据和对应地址（诸如存储操作）的操作。为了进一步确保数据的对应和要在操作中使用的地址，客户端被配置为生成并利用附加符号。该符号至少部分地生成对应于数据的地址。该符号然后与数据相关联并用于表示相应的地址。该符号然后可以由系统内的各种客户端使用来检查建议在数据的操作中使用的地址。

7. 发明授权

US06269426B1 Method for operating a non-blocking hierarchical cache throttle 失效
标题翻译：用于操作非阻塞分级缓存节流阀的方法
公开(公告)号：US06269426B1
公开(公告)日：2001-07-31
申请号：US08881724
申请日：1997-06-24
申请人： Ricky C. Hetherington , Thomas M. Wicki
发明人： Ricky C. Hetherington , Thomas M. Wicki
IPC分类号： G06F1208
CPC分类号： G06F12/0897
摘要： A multi-level cache and method for operation of a multi-level cache generating multiple cache system accesses simultaneously. Each access request includes an address identifying a memory location having data that is a target of the access. A insertion pointer inserts each access request into an entry in a memory scheduling window. Each entry is marked as valid when that entry is ready to be applied to a first cache level. A picker picks valid entries from the memory scheduling window by pointing to the picked entry and applying the address therein to the first cache level. The picking occurs in a free-running mode regardless of whether the accesses hit in the first cache level. A second cache level, receives accesses that have missed in the first cache level. A resource monitor in the second cache level determines when a predetermined number of resources are committed to servicing the accesses that have missed in the first cache level. In response to the monitoring step the second cache level generates a stall signal thereby stalling the picking process.
摘要翻译：用于操作多级缓存的多级缓存和方法，其同时生成多个高速缓存系统访问。每个访问请求包括标识具有作为访问目标的数据的存储器位置的地址。插入指针将每个访问请求插入到内存调度窗口中的条目中。当该条目准备好应用于第一个缓存级别时，每个条目都将被标记为有效。选择器通过指向所选择的条目并将其中的地址应用于第一高速缓存级别从存储器调度窗口中选择有效条目。无论访问是否在第一个高速缓存级别中，都会以自由运行模式进行选择。第二缓存级别，接收在第一高速缓存级别中丢失的访问。第二高速缓存级别中的资源监视器确定预定数量的资源何时被提交到服务于在第一高速缓存级别中错过的访问。响应于监视步骤，第二高速缓存级别产生失速信号，从而停止拾取过程。

8. 发明授权

US5509038A Multi-path data synchronizer system and method 失效
标题翻译：多路数据同步器系统及方法
公开(公告)号：US5509038A
公开(公告)日：1996-04-16
申请号：US223575
申请日：1994-04-06
申请人： Thomas M. Wicki
发明人： Thomas M. Wicki
IPC分类号： H04L7/00 , H04L7/02 , H04L25/36 , H04L25/40
CPC分类号： H04L7/0012 , H04L7/02 , H04L7/0041
摘要： A system and method for transferring data between clock domains operating at substantially the same frequency continuously compares the phase relationship of the clocks of the two domains and retains the current state of comparison at the start of a transfer of a block or frame of data for determining along which one of multiple data paths within the synchronizing circuit the transfer of the data frame will take place. Several data paths with different delays (at least two) transfer the data frame and clock signals. A phase comparator responds to the phase relationship between clocks attaining a value within one or another range of values at the start of a data frame to determine which one of the multiple data paths transfers the data frame.
摘要翻译：用于以基本上相同的频率操作的时钟域之间传送数据的系统和方法持续地比较两个域的时钟的相位关系，并且在用于确定的数据块或数据帧的传送开始时保持当前的比较状态沿同步电路内的多个数据路径中的一个数据帧的传送将发生。具有不同延迟（至少两个）的数据路径传送数据帧和时钟信号。相位比较器响应在数据帧开始时达到一个或另一个值范围内的值的时钟之间的相位关系，以确定多个数据路径中的哪一个传送数据帧。

9. 发明授权

US09285865B2 Dynamic link scaling based on bandwidth utilization 有权
标题翻译：基于带宽利用率的动态链路缩放
公开(公告)号：US09285865B2
公开(公告)日：2016-03-15
申请号：US13539294
申请日：2012-06-29
申请人： Brian F. Keish , Thomas M. Wicki , Sebastian Turullols
发明人： Brian F. Keish , Thomas M. Wicki , Sebastian Turullols
IPC分类号： G06F1/00 , G06F1/32 , G06F13/38 , H04N21/231
CPC分类号： G06F1/3243 , G06F1/32 , G06F1/3203 , G06F1/3209 , G06F1/3253 , G06F1/3287 , G06F13/38 , H04N21/23106 , Y02D10/151 , Y02D10/152
摘要： Systems and methods for reducing power consumption during data transport across multiple processors when link utilization is low. In a multi-node system, at least one of two nodes may indicate low utilization for a given link between them. In response to further determining no enabled link between the two nodes is over utilized, each of the two nodes may remove the given link from consideration for being scheduled to receive data for transfer and turn off the given link when no more transactions are scheduled for the given link. Disabled links may be re-enabled when high utilization is detected on at least one link between the two nodes.
摘要翻译：当链路利用率低时，可以在多个处理器之间传输数据时降低功耗的系统和方法。在多节点系统中，两个节点中的至少一个可以指示它们之间给定链路的低利用率。响应于进一步确定两个节点之间没有启用的链路被过度利用，两个节点中的每一个节点可以将给定链路从考虑中去除以被调度以接收用于传送的数据，并且在没有为给定链接。当在两个节点之间的至少一个链路上检测到高利用率时，可以重新启用禁用链路。

10. 发明授权

US06912628B2 N-way set-associative external cache with standard DDR memory devices 有权
标题翻译：具有标准DDR存储器设备的N路组合外部缓存
公开(公告)号：US06912628B2
公开(公告)日：2005-06-28
申请号：US10127173
申请日：2002-04-22
申请人： Thomas M. Wicki , Koen R. C. Bennebroek
发明人： Thomas M. Wicki , Koen R. C. Bennebroek
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0879 , G06F12/0607 , G06F12/0831 , G06F12/0864 , G06F2212/1016
摘要： A method, cache system, and cache controller are provided. A two-way and n-way cache organization scheme are presented as at least two embodiments of a set-associative external cache that utilizes standard burst memory devices such as DDR (double data rate) memory devices. The set-associative cache organization scheme is designed to fully utilize burst efficiencies during snoop and invalidation operations. Cache lines are interleaved in such a way that a first burst transfer from the cache to the cache controller brings in a plurality of tags.
摘要翻译：提供了一种方法，缓存系统和高速缓存控制器。作为使用诸如DDR（双数据速率）存储器设备的标准突发存储设备的集合关联外部高速缓存的至少两个实施例，呈现双向和n路缓存组织方案。集相关缓存组织方案被设计为在窥探和无效操作期间充分利用突发效率。高速缓存行以这样的方式进行交织，使得从高速缓存到高速缓存控制器的第一突发传送带来多个标签。

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