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1. 发明授权

US06003064A System and method for controlling data transmission between network elements 失效
标题翻译：控制网元之间数据传输的系统和方法
公开(公告)号：US06003064A
公开(公告)日：1999-12-14
申请号：US603913
申请日：1996-02-22
申请人： Thomas M. Wicki , Patrick J. Helland , Jeffrey D. Larson , Albert Mu , Raghu Sastry , Richard L. Schober, Jr.
发明人： Thomas M. Wicki , Patrick J. Helland , Jeffrey D. Larson , Albert Mu , Raghu Sastry , Richard L. Schober, Jr.
IPC分类号： H04L29/08 , H04L12/56 , H04L13/08 , G06F13/12 , G06F13/14
CPC分类号： H04L47/30 , H04L47/10 , H04L47/26
摘要： A system and method for controlling data transmission between two network elements. A first port of a transmitting element is coupled to a second port of a receiving element. The second port includes buffers for temporarily storing received data until the data can be sent to another element. Included in the transmitting element are a received-currently-full register (RCFR), a sent-and-not-received register (SANRR), and a buffer-busy register (BBR). The transmitting element checks its BBR to determine if a buffer in the receiving element is available. The availability of buffers can be determined using a single priority protocol or a multiple priority protocol. If a buffer is available, the transmitting element transmits a data frame to the receiving element and sets the SANRR and the BBR to indicate that a frame has been sent (and that no acknowledgment has been received), that the selected buffer in the receiver is full, and that no additional data frames are to be sent to this buffer until the buffer is empty. When data is received by the receiving element, it is sent to an available buffer. When the data is received by the buffer, the receiving element sets a bit in a currently-full register (CFR) and a bit in a next-message-to-send register (NMTSR). A control signal is transmitted by the data receiving element on the same signal line as data that is being sent from the data receiving element to the data transmitting element. The data receiving element can multiplex the frames being sent in this direction with the control signal. When the transmitting element receives the control signal, it resets a bit associated with a buffer in the SANRR if the bit is set in the SANRR and if the associated bit in the NMTSR portion of the control signal is set.
摘要翻译：一种用于控制两个网络元件之间的数据传输的系统和方法。发射元件的第一端口耦合到接收元件的第二端口。第二端口包括用于临时存储接收到的数据的缓冲器，直到可以将数据发送到另一个元件。包含在发送元件中的是接收当前完整寄存器（RCFR），发送 - 未接收寄存器（SANRR）和缓冲器 - 忙寄存器（BBR）。发送元件检查其BBR以确定接收元件中的缓冲区是否可用。可以使用单一优先级协议或多优先级协议来确定缓冲区的可用性。如果缓冲器可用，则发送元件向接收元件发送数据帧，并将SANRR和BBR设置为指示已经发送了帧（并且没有接收到确认），接收器中所选择的缓冲器是完全，并且在缓冲区为空之前，不会将其他数据帧发送到此缓冲区。当接收元件接收到数据时，它被发送到可用的缓冲器。当数据被缓冲器接收时，接收单元设置当前完整寄存器（CFR）中的位和下一个消息发送寄存器（NMTSR）中的位。控制信号由数据接收元件在与数据接收元件发送到数据发送元件的数据相同的信号线上发送。数据接收元件可以将在该方向上发送的帧与控制信号进行复用。当发送元件接收到控制信号时，如果在SANRR中设置该位，并且控制信号的NMTSR部分中的关联位被置位，则复位与SANRR中的缓冲器有关的位。

2. 发明授权

US5987629A Interconnect fault detection and localization method and apparatus 失效
标题翻译：互连故障检测和定位方法及装置
公开(公告)号：US5987629A
公开(公告)日：1999-11-16
申请号：US45456
申请日：1998-03-20
申请人： Raghu Sastry , Jeffrey D. Larson , Albert Mu , John R. Slice , Richard L. Schober, Jr. , Thomas M. Wicki
发明人： Raghu Sastry , Jeffrey D. Larson , Albert Mu , John R. Slice , Richard L. Schober, Jr. , Thomas M. Wicki
IPC分类号： H04L1/00 , H04L1/08 , H04L1/24 , H04L12/26 , G06F11/00
CPC分类号： H04L1/0057 , H04L1/08 , H04L1/24 , H04L12/2697 , H04L43/50
摘要： A method and apparatus for detecting and isolating an interconnect fault in a packet switched network generates a parity check error code for status messages which are used for flow control in a packet switched network. The packet switched network uses a reverse flow control method wherein status messages are sent locally between adjacent nodes. A receiving node uses status messages to inform an adjacent node of the availability of the input buffers located in the receiving node. Included in the status message is a parity check code that is sent sequentially with the status message using two phases of a clock. The parity check code is a one bit parity check for each bit of the status message. Faults on the local interconnect are detected at the receiving node by performing a one bit parity check on the received status message using the accompanying parity code. Because the status message and the parity check code are transmitted over the same physical bit connections, the one bit parity checks detects any "stuck at" or "open" faults in the link.
摘要翻译：用于检测和隔离分组交换网络中的互连故障的方法和装置为分组交换网络中用于流量控制的状态消息生成奇偶校验错误代码。分组交换网络使用逆向流控制方法，其中状态消息在相邻节点之间本地发送。接收节点使用状态消息来向相邻节点通知位于接收节点中的输入缓冲器的可用性。包括在状态消息中的是奇偶校验码，该状态消息使用两个阶段的时钟与状态消息顺序发送。奇偶校验码是状态消息的每一位的一位奇偶校验。在接收节点通过使用伴随的奇偶校验码对接收到的状态消息执行一位奇偶校验来检测局部互连上的故障。由于状态消息和奇偶校验码通过相同的物理位连接传输，所以一位奇偶校验检测检测链路中的任何“卡住”或“打开”故障。

3. 发明授权

US5768300A Interconnect fault detection and localization method and apparatus 失效
公开(公告)号：US5768300A
公开(公告)日：1998-06-16
申请号：US603911
申请日：1996-02-22
申请人： Raghu Sastry , Jeffrey D. Larson , Albert Mu , John R. Slice , Richard L. Schober, Jr. , Thomas M. Wicki
发明人： Raghu Sastry , Jeffrey D. Larson , Albert Mu , John R. Slice , Richard L. Schober, Jr. , Thomas M. Wicki
IPC分类号： H04L1/00 , H04L1/08 , H04L1/24 , H04L12/26 , G06F11/10 , H03M13/00
CPC分类号： H04L1/0057 , H04L1/08 , H04L1/24 , H04L12/2697 , H04L43/50
摘要： A method and apparatus for detecting and isolating an interconnect fault in a packet switched network generates a parity check error code for status messages which are used for flow control in a packet switched network. The packet switched network uses a reverse flow control method wherein status messages are sent locally between adjacent nodes. A receiving node uses status messages to inform an adjacent node of the availability of the input buffers located in the receiving node. Included in the status message is a parity check code that is sent sequentially with the status message using two phases of a clock. The parity check code is a one bit parity check for each bit of the status message. Faults on the local interconnect are detected at the receiving node by performing a one bit parity check on the received status message using the accompanying parity code. Because the status message and the parity check code are transmitted over the same physical bit connections, the one bit parity checks detects any "stuck at" or "open" faults in the link.

4. 发明授权

US5838684A Low latency, high clock frequency plesioasynchronous packet-based crossbar switching chip system and method 失效
标题翻译：低延迟，高时钟频率同步分组交叉开关芯片系统和方法
公开(公告)号：US5838684A
公开(公告)日：1998-11-17
申请号：US603926
申请日：1996-02-22
申请人： Thomas M. Wicki , Jeffrey D. Larson , Albert Mu , Raghu Sastry
发明人： Thomas M. Wicki , Jeffrey D. Larson , Albert Mu , Raghu Sastry
IPC分类号： H04L12/56
CPC分类号： H04L49/253 , H04L49/101 , H04L49/1546 , H04L49/254 , H04L49/3018
摘要： An plesioasynchronous and asynchronous router circuit communicates with neighboring router circuits and nodes. Each of the router circuits includes a plurality of input ports for receiving frames of data and a plurality of output ports for transmitting frames of data. Each router circuit further includes a plurality of input buffers for storing frames of data received at an input port, and an arbiter system for choosing one of several input buffers associated with a particular one of said output ports. The arbiter system includes a plurality of arbiter subsystems associated with corresponding ones of said plurality of output ports. The plesioasynchronous and asynchronous router circuit further includes a crossbar switch for connecting an arbiter selected input buffer with a particular one of said output ports.
摘要翻译：异步和异步路由器电路与相邻的路由器电路和节点进行通信。每个路由器电路包括用于接收数据帧的多个输入端口和用于发送数据帧的多个输出端口。每个路由器电路还包括用于存储在输入端口处接收的数据帧的多个输入缓冲器和用于选择与特定一个所述输出端口相关联的多个输入缓冲器之一的仲裁器系统。仲裁器系统包括与所述多个输出端口中的相应的输出端口相关联的多个仲裁器子系统。同步和异步路由器电路还包括用于将仲裁器选择的输入缓冲器与特定的所述输出端口连接的交叉开关。

5. 发明授权

US5991296A Crossbar switch and method with reduced voltage swing and no internal blocking data path 失效
标题翻译：交叉开关和方法具有降低的电压摆幅和无内部阻塞数据路径
公开(公告)号：US5991296A
公开(公告)日：1999-11-23
申请号：US604920
申请日：1996-02-22
申请人： Albert Mu , Jeffrey D. Larson
发明人： Albert Mu , Jeffrey D. Larson
IPC分类号： H04L12/56 , H04Q3/52
CPC分类号： H04Q3/523 , H04L49/25 , H04L49/101 , H04L49/205 , H04L49/254 , H04L49/3018
摘要： A switch system and method transfer a data packet from a source data port to one or more destination data ports through a switch. The system comprises a source input buffer, a first and a second source input path, a first and a second output path and at least one crosspoint circuit. The source input buffer includes a first and a second data section. The first and the second data sections are coupled to the first and the second input paths respectively. The first and the second input paths couple through the crosspoint circuits at each intersection with the first and the second output paths. The method includes loading the data packets into data sections of an input buffer, transferring each data packet across an input path dedicated for each data section, transmitting each data packet over its input path, and switching the data from the input path to the output path based on a voltage differential. A crosspoint circuit in the switch system includes a first and a second reduced voltage swing line, a first and a second transistor circuit for each data input path and a sense amplifier for a data port. The first reduced voltage swing line is coupled to the first transistor circuit, the second reduced voltage swing line is coupled to the second transistor circuit and both reduced voltage swing lines are connected to the sense amplifier. The method of the unit comprises the steps of charging a first and a second reduced voltage swing line to a predetermined voltage, discharging the voltage from the first reduced voltage swing line, maintaining the voltage in the second voltage line, receiving a clock signal at the sense amplifier, and generating an output signal based on a voltage differential between the voltage lines.
摘要翻译：交换机系统和方法通过交换机将数据分组从源数据端口传送到一个或多个目的数据端口。该系统包括源输入缓冲器，第一和第二源输入路径，第一和第二输出路径以及至少一个交叉点电路。源输入缓冲器包括第一和第二数据段。第一和第二数据部分分别耦合到第一和第二输入路径。第一和第二输入路径在与第一和第二输出路径的每个交叉处耦合通过交叉点电路。该方法包括将数据分组加载到输入缓冲器的数据部分中，通过专用于每个数据部分的输入路径传送每个数据分组，在其输入路径上传送每个数据分组，并将数据从输入路径切换到输出路径基于电压差。开关系统中的交叉点电路包括第一和第二降压摆线，用于每个数据输入路径的第一和第二晶体管电路以及用于数据端口的读出放大器。第一降压摆动线耦合到第一晶体管电路，第二降压摆线与第二晶体管电路耦合，并且两个还原电压摆幅线连接到读出放大器。该单元的方法包括以下步骤：将第一和第二降压摆幅线充电至预定电压，对来自第一降压摆幅线的电压进行放电，保持第二电压线中的电压，接收时钟信号读出放大器，并且基于电压线之间的电压差产生输出信号。

6. 发明授权

US06490213B1 Crossbar switch and method with crosspoint circuit 失效
标题翻译：交叉开关和交叉点电路方法
公开(公告)号：US06490213B1
公开(公告)日：2002-12-03
申请号：US09419702
申请日：1999-10-14
申请人： Albert Mu , Jeffrey D. Larson
发明人： Albert Mu , Jeffrey D. Larson
IPC分类号： G11C702
CPC分类号： H04Q3/523 , H04L49/101 , H04L49/205 , H04L49/25 , H04L49/254 , H04L49/3018
摘要： A switch system and method transfer a data packet from a source data port to one or more destination data ports through a switch. The system includes at least one crosspoint circuit. A crosspoint circuit in the switch system includes a first and a second reduced voltage swing line, a first and a second transistor circuit for each data input path and a sense amplifier for a data port. The first reduced voltage swing line is coupled to the first transistor circuit, the second reduced voltage swing line is coupled to the second transistor circuit and both reduced voltage swing lines are connected to the sense amplifier. A method for transferring data using a crosspoint circuit includes a charging first voltage line and a second voltage line to a predetermined voltage level, discharging the predetermined voltage level in the first voltage line, maintaining the predetermined voltage level in the second voltage line concurrently with the discharging step, receiving a high clock signal at a sense amplifier, and generating an output signal based on a differential voltage level at the arrival of the clock signal.
摘要翻译：交换机系统和方法通过交换机将数据分组从源数据端口传送到一个或多个目的数据端口。该系统包括至少一个交叉点电路。开关系统中的交叉点电路包括第一和第二降压摆线，用于每个数据输入路径的第一和第二晶体管电路以及用于数据端口的读出放大器。第一降压摆动线耦合到第一晶体管电路，第二降压摆线与第二晶体管电路耦合，并且两个还原电压摆幅线连接到读出放大器。使用交叉点电路传送数据的方法包括充电第一电压线和第二电压线到预定电压电平，放电第一电压线中的预定电压电平，同时保持第二电压线中的预定电压电平放电步骤，在感测放大器处接收高时钟信号，以及在时钟信号到达时基于差分电压电平产生输出信号。

7. 发明授权

US06684281B1 Fast delivery of interrupt message over network 有权
标题翻译：通过网络快速传递中断消息
公开(公告)号：US06684281B1
公开(公告)日：2004-01-27
申请号：US09705451
申请日：2000-11-02
申请人： Hirohide Sugahara , Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie
发明人： Hirohide Sugahara , Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A computer network system and a method for fast delivery of an interrupt message over a computer network enables a first processor coupled to the computer network to very quickly send an interrupt message to a second processor coupled to the computer network, by directly writing the interrupt message to a doorbell address range associated with the second processor in the PCI memory space of a first PCI bus to which the first processor is coupled. The doorbell address range is mapped to a doorbell space in the PCI memory space of a second PCI bus to which the second processor is coupled. The first PCI bus is coupled to the computer network through a first PCI network adaptor, which processes the write transaction and send it to the network. The second PCI bus is coupled to the computer network through a second PCI network adaptor, which receives the write transaction from the network and transforms the write transaction into an interrupt message to the second processor.
摘要翻译：计算机网络系统和用于通过计算机网络快速传递中断消息的方法使得耦合到计算机网络的第一处理器能够通过直接写入中断消息来非常快速地向耦合到计算机网络的第二处理器发送中断消息涉及与第一处理器耦合到的第一PCI总线的PCI存储器空间中与第二处理器相关联的门铃地址范围。门铃地址范围被映射到与第二处理器耦合到的第二PCI总线的PCI存储器空间中的门铃空间。第一个PCI总线通过第一个PCI网络适配器耦合到计算机网络，该PCI网络适配器处理写入事务并将其发送到网络。第二PCI总线通过第二PCI网络适配器耦合到计算机网络，第二PCI网络适配器从网络接收写入事务，并将写入事务转换为中断消息给第二处理器。

8. 发明授权

US06678758B2 Dynamic queuing for read/write requests 有权
标题翻译：动态排队读/写请求
公开(公告)号：US06678758B2
公开(公告)日：2004-01-13
申请号：US09778649
申请日：2001-02-05
申请人： Jeffrey D. Larson , Hirohide Sugahara , Takashi Miyoshi , Takeshi Horie
发明人： Jeffrey D. Larson , Hirohide Sugahara , Takashi Miyoshi , Takeshi Horie
IPC分类号： G06F1314
CPC分类号： G06F13/387
摘要： A PCI (peripheral component interconnect) network adaptor manages read/write requests through the establishment of dynamic queues. The PCI network adaptor establishes a unique queue for each destination node that enables the requests for each node to be processed separately. The PCI network adaptor determines whether a remote read/write request should be added to the linked list for the destination node of the request or whether the request should be rejected. If the number of pending requests for the destination node is below a predetermined threshold and the entire buffer is not full, then the request is added to the linked list for the destination node. Otherwise, the request is rejected. For write requests, if the request is added to the linked list for the destination node, then any pending read requests for that node are aborted.
摘要翻译： PCI（外围组件互连）网络适配器通过建立动态队列来管理读/写请求。 PCI网络适配器为每个目标节点建立一个唯一的队列，使每个节点的请求能够单独处理。 PCI网络适配器确定是否应将远程读/写请求添加到请求的目标节点的链接列表中，还是请求被拒绝。如果目的地节点的未决请求数量低于预定阈值并且整个缓冲器未满，则将该请求添加到目的地节点的链表。否则，请求被拒绝。对于写入请求，如果将请求添加到目标节点的链接列表，则该节点的任何未决读取请求将被中止。

9. 发明授权

US06877039B2 Simplified pipeline writes over a network 有权
标题翻译：简化的流水线通过网络写入
公开(公告)号：US06877039B2
公开(公告)日：2005-04-05
申请号：US09842481
申请日：2001-04-25
申请人： Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie , Hirohide Sugahara
发明人： Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie , Hirohide Sugahara
IPC分类号： H04L12/40 , H04L12/28 , H04L29/06 , H04L29/08 , G06F15/16 , G06F13/36 , G08C25/02
CPC分类号： H04L29/06 , H04L69/324
摘要： A system and method are provided for efficiently writing data from one bus device to another bus device across a network. Data packets to be transmitted are ordered and assigned sequence numbers and expected sequence numbers. The expected sequence number of a data packet corresponds to the sequence number of the data packet immediately prior to the current data packet. When a data packet arrives at the receiving bus, its expected sequence number is compared against the sequence numbers of the previous data packets received. If the previously-received data packet bears the sequence number corresponding to the expected sequence number of the newly arrived data packet, the newly arrived data is stored, and an acknowledgement is sent. If a match cannot be found then a retry request message is sent.
摘要翻译：提供了一种系统和方法，用于通过网络有效地将数据从一个总线设备写入另一总线设备。要发送的数据包被排序并分配序列号和预期的序列号。数据分组的期望序列号对应于紧接当前数据分组之前的数据分组的序列号。当数据分组到达接收总线时，将其预期序列号与接收的先前数据分组的序列号进行比较。如果先前接收到的数据分组具有与新到达的数据分组的预期序列号相对应的序列号，则存储新到达的数据，并发送确认。如果无法找到匹配项，则发送重试请求消息。

10. 发明授权

US06901451B1 PCI bridge over network 失效
标题翻译： PCI桥接网络
公开(公告)号：US06901451B1
公开(公告)日：2005-05-31
申请号：US09703477
申请日：2000-10-31
申请人： Takashi Miyoshi , Jeffrey D. Larson , Hirohide Sugahara , Takeshi Horie
发明人： Takashi Miyoshi , Jeffrey D. Larson , Hirohide Sugahara , Takeshi Horie
IPC分类号： G06F13/36 , G06F13/40 , G06F15/16 , H04L12/40
CPC分类号： G06F13/4027
摘要： One embodiment of the present invention provides a method for communicating transaction request information from a PCI environment over a network. Another embodiment of the present invention provides a method for communicating request packet information from a network to a PCI environment. Another embodiment of the present invention provides a system for communicating transaction request information from a PCI environment over a network. Another embodiment of the present invention provides a system for communicating request packet information from a network to a PCI environment.
摘要翻译：本发明的一个实施例提供了一种用于通过网络从PCI环境传送交易请求信息的方法。本发明的另一实施例提供了一种用于将请求分组信息从网络传送到PCI环境的方法。本发明的另一实施例提供一种用于通过网络从PCI环境传送交易请求信息的系统。本发明的另一个实施例提供一种用于将请求分组信息从网络传送到PCI环境的系统。

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