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    • 6. 发明授权
    • System and method for dynamic network topology exploration
    • 动态网络拓扑探索的系统与方法
    • US5740346A
    • 1998-04-14
    • US605676
    • 1996-02-22
    • Thomas M. WickiPatrick J. HellandWolf-Dietrich WeberWinfried W. Wilcke
    • Thomas M. WickiPatrick J. HellandWolf-Dietrich WeberWinfried W. Wilcke
    • H04L12/56
    • H04L45/02
    • A system and method dynamically determines the topology of a source node routing network while having a minimal effect on network performance and without requiring expensive hardware to implement. A source node generates a ping frame. The source node transmits the ping frame to a first source router that is coupled to the source node. The first router transparently identifies the frame as a ping frame and creates an echo frame that is transmitted back to the source node. The first router identifies the port from which the ping frame is received and places this information in the header of the echo frame along with an echo frame identifier. The source node receives the echo frame and identifies routers and nodes to which a ping frame has not been sent based upon the connectivity information in the received echo frame. The source node continue generating and transmitting ping frame to all nodes and routers in the network. The source node identifies loops in the topology to avoid repetitive checking and identifies link and router failures. The topology exploration technique is transparent to the routers The topology exploration techique can be implemented during slow traffic periods with no increase in network latency or the technique can be implemented during high traffic periods and result in only a minimal increase in system latency because ping frames are small and are transparently sent to the control frame handler of the destination router or node.
    • 系统和方法动态地确定源节点路由网络的拓扑,同时对网络性能影响最小,而不需要昂贵的硬件来实现。 源节点生成ping帧。 源节点将ping帧发送到耦合到源节点的第一源路由器。 第一个路由器将该帧透明地识别为一个ping帧,并创建一个发送回源节点的回波帧。 第一个路由器识别从其接收ping帧的端口,并将该信息与回波帧标识符一起放置在回波帧的报头中。 根据所接收的回波帧中的连通性信息,源节点接收回波帧并识别尚未发送ping帧的路由器和节点。 源节点继续生成并发送Ping帧到网络中的所有节点和路由器。 源节点标识拓扑中的循环,以避免重复检查,并识别链路和路由器故障。 拓扑探索技术对于路由器是透明的。拓扑探索技术可以在较慢的流量周期内实现,而不会增加网络延迟,或者在高流量时段内可以实现该技术,并且只能使系统延迟最小化,因为ping帧 并且被透明地发送到目的地路由器或节点的控制帧处理器。
    • 8. 发明授权
    • Asynchronous packet switching
    • 异步分组交换
    • US5959995A
    • 1999-09-28
    • US605677
    • 1996-02-22
    • Thomas M. WickiPatrick J. HellandTakeshi ShimizuWolf-Dietrich WeberWinfried W. Wilcke
    • Thomas M. WickiPatrick J. HellandTakeshi ShimizuWolf-Dietrich WeberWinfried W. Wilcke
    • G06F15/17H04L12/56H04J3/24
    • H04L45/00H04L45/34
    • A multiprocessor system includes a plurality of nodes and an interconnect that includes routers. Each node includes a reliable packet mover and a fast frame mover. The reliable packet mover provides packets to the fast frame mover which adds routing information to the packet to form a frame. The route to each node is predetermined. The frame is provided to the routers which delete the route from the routing information. If the frame is lost while being routed, the router discards the frame. If the packet is received at a destination node, the reliable packet mover in that node sends an acknowledgment to the source node if the packet passes an error detection test. The reliable packet mover in the source node resends the packet if it does not receive an acknowledgment in a predetermined time. The fast frame mover randomly selects the route from a plurality of predetermined routes to the destination node according to a probability distribution.
    • 多处理器系统包括多个节点和包括路由器的互连。 每个节点包括可靠的分组移动器和快速帧移动器。 可靠的分组移动器向快速帧移动器提供分组,其将路由信息添加到分组以形成帧。 到每个节点的路由是预定的。 该帧被提供给从路由信息中删除路由的路由器。 如果在路由时帧丢失,路由器将丢弃帧。 如果在目的地节点处接收到分组,则如果分组通过错误检测测试,则该节点中的可靠分组移动器向源节点发送确认。 如果源节点中的可靠的分组移动器在预定时间内没有接收到确认,则重新发送分组。 快速帧移动器根据概率分布从多个预定路由到目的地节点随机选择路由。
    • 9. 发明授权
    • Test circuit for differential cascode voltage switch
    • 差分共源共栅电压开关测试电路
    • US4656417A
    • 1987-04-07
    • US759804
    • 1985-07-29
    • Edward S. KirkpatrickEric P. KronstadtRobert K. MontoyeWinfried W. Wilcke
    • Edward S. KirkpatrickEric P. KronstadtRobert K. MontoyeWinfried W. Wilcke
    • H03K17/00G01R31/28G01R31/3185G06F11/00G06F11/267
    • G06F11/2215G01R31/318541G01R31/318572G01R31/31858G06F11/0751
    • An improved testing and checking circuit for a Differential Cascode Voltage Switch which uses N-devices for both the invalid (0,0) and (1,1) state detection of Q and Q switch signals, and uses decoupling pass devices for sampling the data at the fall of the system C-clock, additionally allowing simultaneous pre-charging and error detection. The testing and checking circuit is incorporated in a hierarchical scheme, which uses the system C-clock for input to the latches, decoupling of the buffers, and pulling up and down the error lines. The error fault is held in a system latch. Also described is a circuit scheme which self tests a large macro using only the C-clock and latches the result in a single latch. More particularly, the described circuit employs the Q and Q signals in a NOR configuration, thus detecting if neither signal has sufficient voltage to pull down the load device which consists of a P-device whose gate is attached to the C-clock. The resulting signal is run to a gate in parallel with the two N-devices. Thus, the two low signals allow this NOR gate to rise and produce a pulldown leg to an error line. An invalid signal condition is detected if either both signals are sufficiently high to turn on an N-device or neither signal is high enough to turn on an N-device. Therefore, the described circuit registers a failure if and only if there is the potential for a tree with the same inputs to enter an invalid state.
    • 用于差分串联电压开关的改进的测试和检查电路,其使用N个器件用于Q和& upbar&Q开关信号的无效(0,0)和(1,1)状态检测,并使用去耦通设备进行采样 数据在系统C-clock掉落时,另外允许同时进行预充电和错误检测。 测试和检查电路并入分层方案,其使用系统C时钟输入到锁存器,解耦缓冲器以及上下错误线。 错误故障保存在系统锁存器中。 还描述了一种电路方案,其仅使用C时钟自检测大宏,并将结果锁存在单个锁存器中。 更具体地,所描述的电路采用NOR配置中的Q和& Upbar&Q信号,从而检测两个信号是否没有足够的电压来下拉由栅极连接到C时钟的P装置构成的负载装置。 结果信号与两个N器件并行运行到门。 因此,两个低信号允许该或非门上升并产生到故障线的下拉腿。 如果两个信号都足够高以接通N装置,或者两个信号都不足够高以打开N装置,则检测到无效信号条件。 因此,当且仅当存在具有相同输入的树进入无效状态的可能性时,所描述的电路注册失败。