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1. 发明授权

US09852080B2 Efficiently generating selection masks for row selections within indexed address spaces 有权
公开(公告)号：US09852080B2
公开(公告)日：2017-12-26
申请号：US15087077
申请日：2016-03-31
申请人： QUALCOMM Incorporated
发明人： David Paul Hoff , Milind Ram Kulkarni , Benjamin John Bowers
IPC分类号： G06F12/10 , G06F12/0879 , G06F12/0895 , G06F1/06 , G06F12/14 , G06F12/1027
CPC分类号： G06F12/10 , G06F1/06 , G06F12/0879 , G06F12/0895 , G06F12/1027 , G06F12/1441 , G06F2212/1016 , G06F2212/1041 , G06F2212/65
摘要： Efficiently generating selection masks for row selections within indexed address spaces is disclosed. In this regard, in one aspect, an indexed array circuit is provided, comprising a start indicator that indicates a start indexed array row of a row selection, and an end indicator that indicates an end indexed array row of the row selection. The indexed array circuit further comprises a plurality of indexed array rows ordered in a logical sequence, each comprising a row-level compare circuit. Each row-level compare circuit is configured to generate a selection mask indicator based on a first parallel comparison of subsets of bits of a logical address of the indexed array row with corresponding subsets of bits of the start indicator, and a second parallel comparison of subsets of bits of the logical address of the indexed array row with corresponding subsets of bits of the end indicator.

2. 发明申请

US20170052900A1 EFFICIENTLY GENERATING SELECTION MASKS FOR ROW SELECTIONS WITHIN INDEXED ADDRESS SPACES 有权
标题翻译：在索引地址空间中有效选择选择面
公开(公告)号：US20170052900A1
公开(公告)日：2017-02-23
申请号：US15087077
申请日：2016-03-31
申请人： QUALCOMM Incorporated
发明人： David Paul Hoff , Milind Ram Kulkarni , Benjamin John Bowers
IPC分类号： G06F12/10 , G06F1/06
CPC分类号： G06F12/10 , G06F1/06 , G06F12/0879 , G06F12/0895 , G06F12/1027 , G06F12/1441 , G06F2212/1016 , G06F2212/1041 , G06F2212/65
摘要： Efficiently generating selection masks for row selections within indexed address spaces is disclosed. In this regard, in one aspect, an indexed array circuit is provided, comprising a start indicator that indicates a start indexed array row of a row selection, and an end indicator that indicates an end indexed array row of the row selection. The indexed array circuit further comprises a plurality of indexed array rows ordered in a logical sequence, each comprising a row-level compare circuit. Each row-level compare circuit is configured to generate a selection mask indicator based on a first parallel comparison of subsets of bits of a logical address of the indexed array row with corresponding subsets of bits of the start indicator, and a second parallel comparison of subsets of bits of the logical address of the indexed array row with corresponding subsets of bits of the end indicator.
摘要翻译：公开了在索引的地址空间内高效地生成用于行选择的选择掩码。在这方面，在一个方面，提供了一种索引阵列电路，包括指示行选择的开始索引的数组行的开始指示符和指示行选择的结束索引的数组行的结束指示符。索引阵列电路还包括以逻辑序列排序的多个索引阵列行，每个包括行级比较电路。每个行级比较电路被配置为基于索引数组行的逻辑地址的位的子集与开始指示符的相应的子集的第一并行比较来生成选择掩码指示符，以及子集的第二并行比较的索引数组行的逻辑地址的位与终端指示符的相应的子集。

3. 发明申请

US20170031829A1 Advance Cache Allocator 审中-公开
标题翻译：高级缓存分配器
公开(公告)号：US20170031829A1
公开(公告)日：2017-02-02
申请号：US14811436
申请日：2015-07-28
申请人： Futurewei Technologies, Inc.
发明人： Sushma Wokhlu , Lee McFearin , Alan Gatherer , Ashish Shrivastava , Peter Yifey Yan
IPC分类号： G06F12/08
CPC分类号： G06F12/0879 , G06F12/0862 , G06F12/0864 , G06F12/0895 , G06F2212/60 , G06F2212/6026 , G06F2212/6028
摘要： Systems and techniques for advance cache allocation are described. A described technique includes selecting a job from a plurality of jobs; selecting a processor core from a plurality of processor cores to execute the selected job; receiving a message which describes future memory accesses that will be generated by the selected job; generating a memory burst request based on the message; performing the memory burst request to load data from a memory to at least a dedicated portion of a cache, the cache corresponding to the selected processor core; and starting the selected job on the selected processor core. The technique can include performing an action indicated by a send message to write one or more values from another dedicated portion of the cache to the memory.
摘要翻译：描述了用于提前高速缓存分配的系统和技术。所描述的技术包括从多个作业中选择作业; 从多个处理器核心选择处理器核心以执行所选择的作业; 接收描述将由所选作业生成的未来存储器访问的消息; 基于所述消息产生存储器突发请求; 执行所述存储器突发请求以将数据从存储器加载到高速缓存的至少专用部分，所述高速缓存对应于所选择的处理器核; 并在所选的处理器核心上启动所选作业。该技术可以包括执行由发送消息指示的动作，以将一个或多个值从高速缓存的另一个专用部分写入存储器。

4. 发明授权

US09396783B2 Magnetic random access memory with dynamic random access memory (DRAM)-like interface 有权
标题翻译：具有动态随机存取存储器（DRAM）的接口的磁性随机存取存储器
公开(公告)号：US09396783B2
公开(公告)日：2016-07-19
申请号：US15009367
申请日：2016-01-28
申请人： Avalanche Technology, Inc.
发明人： Siamack Nemazie
IPC分类号： G11C11/16 , G06F13/28 , G06F12/08
CPC分类号： G11C11/1675 , G06F12/0879 , G06F13/28 , G11C7/10 , G11C7/22 , G11C11/1673 , G11C11/1693
摘要： A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.
摘要翻译：存储器件包括用于在突发写入操作期间存储数据突发的磁存储器单元。每个数据突发包括顺序数据单元，其中每个数据单元在时钟周期被接收，并且在突发写入操作期间写入，其中在多个时钟周期期间执行突发写入操作。此外，存储器件包括耦合到磁存储器单元的掩模寄存器，其在突发写入操作期间产生写掩码以禁止或使能写数据的数据单元。此外，存储器件允许在接收要写入的数据的突发的数据单元或提供读取数据的同时开始下一个突发写入操作。

5. 发明授权

US09286218B2 Word line auto-booting in a spin-torque magnetic memory having local source lines 有权
标题翻译：字线在具有本地源极线的自旋转矩磁存储器中自动启动
公开(公告)号：US09286218B2
公开(公告)日：2016-03-15
申请号：US14495151
申请日：2014-09-24
申请人： Everspin Technologies, Inc.
发明人： Thomas Andre , Syed M. Alam
IPC分类号： G11C7/12 , G11C11/16 , G11C7/08 , G06F12/08 , G11C11/4094 , G11C11/419 , G11C11/4091 , G11C11/56
CPC分类号： G11C11/1675 , G06F12/0806 , G06F12/0879 , G06F2212/62 , G11C7/1018 , G11C7/1045 , G11C7/12 , G11C7/22 , G11C11/16 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C11/4091 , G11C11/4094 , G11C11/419 , G11C11/5607 , Y02D10/13
摘要： In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to conserve power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.
摘要翻译：在包括本地源线的自旋扭矩磁随机存取存储器（MRAM）中，字线的自动引导用于通过在写入操作期间重新使用已经存在的驱动多个位线的电荷来节省功耗。通过首先将字线驱动到第一字线电压来实现自动启动。经过这样的驾驶，字线隔离。随后驱动电容耦合到字线的多个位线使得字线电压增加到期望的水平，以允许足够的电流流过选定的存储器单元以将信息写入所选存储单元。另外的实施例包括使用能够进一步升高或保持隔离字线处于所需电压电平的补充电压提供器。

6. 发明授权

US09251882B2 Magnetic random access memory with dynamic random access memory (DRAM)-like interface 有权
标题翻译：具有动态随机存取存储器（DRAM）的接口的磁性随机存取存储器
公开(公告)号：US09251882B2
公开(公告)日：2016-02-02
申请号：US13303947
申请日：2011-11-23
申请人： Siamack Nemazie
发明人： Siamack Nemazie
IPC分类号： G11C11/16 , G11C7/10 , G11C7/22 , G06F12/08
CPC分类号： G11C11/1675 , G06F12/0879 , G06F13/28 , G11C7/10 , G11C7/22 , G11C11/1673 , G11C11/1693
摘要： A memory device includes a magnetic memory unit for storing a burst of data during burst write operations, each burst of data includes, sequential data units with each data unit being received at a clock cycle, and written during a burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data, furthermore the memory device allowing burst write operation to begin while receiving data units of the next burst of data to be written or providing read data.
摘要翻译：存储器件包括用于在脉冲串写入操作期间存储数据突发的磁存储器单元，每个突发数据包括在每个数据单元以时钟周期接收的顺序数据单元，并且在突发写入操作期间写入，写操作在多个时钟周期内执行。此外，存储器件包括耦合到磁存储器单元的掩模寄存器，其在突发写入操作期间产生写掩码以禁止或启用写数据的数据单元，此外，存储器件允许突发写操作开始同时接收数据单元要写入或提供读取数据的下一个数据组。

7. 发明授权

US08972995B2 Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads 有权
标题翻译：同时执行每个线程以及线程内和跨两个或多个线程的每个标签内存访问调度的设备和方法
公开(公告)号：US08972995B2
公开(公告)日：2015-03-03
申请号：US12852355
申请日：2010-08-06
申请人： Krishnan Srinivasan , Ruben Khazhakyan , Harutyan Aslanyan , Drew E. Wingard , Chien-Chun Chou
发明人： Krishnan Srinivasan , Ruben Khazhakyan , Harutyan Aslanyan , Drew E. Wingard , Chien-Chun Chou
IPC分类号： G06F9/46 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34 , G06F15/00 , G06F15/76 , G06F9/52
CPC分类号： G06F9/526 , G06F12/0879 , G06F12/0882
摘要： A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.
摘要翻译：集成电路包括启动器知识产权（IP）核心，目标IP核，互连以及标签和线程逻辑的方法，装置和系统。目标IP核可以包括耦合到发起者IP核的存储器。另外，互连可以允许集成电路在一个或多个启动器知识产权（IP）核心和耦合到互连的一个或多个目标IP核之间传送事务。标签和线程逻辑可以被配置为同时执行线程内和跨多个线程的每线程和每标签内存访问调度，使得标签和线程逻辑管理标签和线程以允许每标签和每个线程调度的内存从发起者IP内核访问来自发起者IP核的请求的初始发布顺序的顺序的请求。

8. 发明授权

US08468278B2 Methods and apparatuses for flushing write-combined data from a buffer 有权
标题翻译：从缓冲区冲洗写入组合数据的方法和装置
公开(公告)号：US08468278B2
公开(公告)日：2013-06-18
申请号：US11966760
申请日：2007-12-28
申请人： Sivakumar Radhakrishnan , Siva Balasubramanian , William T. Futral , Sujoy Sen , Gregory D. Cummings , Kenneth C. Creta , David C. Lee
发明人： Sivakumar Radhakrishnan , Siva Balasubramanian , William T. Futral , Sujoy Sen , Gregory D. Cummings , Kenneth C. Creta , David C. Lee
IPC分类号： G06F13/00
CPC分类号： G06F13/1631 , G06F12/0831 , G06F12/0879 , G06F12/0897 , H04L69/12
摘要： Methods and apparatuses for flushing write-combined data from a buffer within a memory to an input/output (I/O) device.
摘要翻译：将写入组合数据从存储器中的缓冲器冲洗到输入/输出（I / O）设备的方法和装置。

9. 发明申请

US20100153657A1 OPERATION OF AN INPUT/OUTPUT LINK 有权
标题翻译：输入/输出链路的操作
公开(公告)号：US20100153657A1
公开(公告)日：2010-06-17
申请号：US12337013
申请日：2008-12-17
申请人： Pavel Vasek , Matthew B. Lovell
发明人： Pavel Vasek , Matthew B. Lovell
IPC分类号： G06F12/08
CPC分类号： G06F12/0879
摘要： Included are embodiments for facilitating operation of an input/output (I/O) link. At least one embodiment of a method includes receiving a first cache line from a memory controller and determining whether the first cache line corresponds to a first portion of data. Some embodiments include, when the first cache line corresponds to the first portion of data, determining whether a second cache line is received and when the second cache line is not received, processing the first cache line. Similarly, some embodiments include when the first cache line does not correspond to the first portion of data, waiting for a cache line that does correspond to the first portion of data.
摘要翻译：包括用于促进输入/输出（I / O）链路的操作的实施例。方法的至少一个实施例包括从存储器控制器接收第一高速缓存行并且确定第一高速缓存线是否对应于数据的第一部分。一些实施例包括当第一高速缓存行对应于数据的第一部分时，确定是否接收到第二高速缓存行并且当第二高速缓存行未被接收时，处理第一高速缓存行。类似地，一些实施例包括当第一高速缓存行不对应于数据的第一部分时，等待对应于数据的第一部分的高速缓存行。

10. 发明申请

US20090063729A1 System for Supporting Partial Cache Line Read Operations to a Memory Module to Reduce Read Data Traffic on a Memory Channel 有权
标题翻译：用于支持部分高速缓存行读取操作到内存模块以减少内存通道读取数据流量的系统
公开(公告)号：US20090063729A1
公开(公告)日：2009-03-05
申请号：US11848312
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F3/00
CPC分类号： G06F13/28 , G06F11/1048 , G06F12/0879 , G06F12/0888 , G06F13/1684
摘要： A memory system is provided that supports partial cache line read operations to a memory module to reduce read data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub comprises burst logic integrated in the memory hub device. The burst logic determines an amount of read data to be transmitted from the set of memory devices and generates a burst length field corresponding to the amount of read data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of read data that is transmitted using the burst length field. The memory hub device transmits the amount of read data that is equal to or less than a conventional data burst amount of data.
摘要翻译：提供了一种存储器系统，其支持对存储器模块的部分高速缓存行读取操作以减少存储器通道上的读取数据流量。存储器系统包括集成在存储器模块中的存储器集线器设备和耦合到存储器集线器设备的一组存储器设备。存储器集线器包括集成在存储器集线器设备中的突发逻辑。突发逻辑确定要从该组存储器件发送的读取数据量，并产生与读取数据量对应的突发长度字段。存储器集线器还包括集成在存储器集线器设备中的存储器集线器控制器。存储器集线器控制器控制使用突发长度字段发送的读取数据量。存储器集线器设备发送等于或小于常规数据突发数据量的读取数据量。

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