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1. 发明授权

US5768300A Interconnect fault detection and localization method and apparatus 失效
公开(公告)号：US5768300A
公开(公告)日：1998-06-16
申请号：US603911
申请日：1996-02-22
申请人： Raghu Sastry , Jeffrey D. Larson , Albert Mu , John R. Slice , Richard L. Schober, Jr. , Thomas M. Wicki
发明人： Raghu Sastry , Jeffrey D. Larson , Albert Mu , John R. Slice , Richard L. Schober, Jr. , Thomas M. Wicki
IPC分类号： H04L1/00 , H04L1/08 , H04L1/24 , H04L12/26 , G06F11/10 , H03M13/00
CPC分类号： H04L1/0057 , H04L1/08 , H04L1/24 , H04L12/2697 , H04L43/50
摘要： A method and apparatus for detecting and isolating an interconnect fault in a packet switched network generates a parity check error code for status messages which are used for flow control in a packet switched network. The packet switched network uses a reverse flow control method wherein status messages are sent locally between adjacent nodes. A receiving node uses status messages to inform an adjacent node of the availability of the input buffers located in the receiving node. Included in the status message is a parity check code that is sent sequentially with the status message using two phases of a clock. The parity check code is a one bit parity check for each bit of the status message. Faults on the local interconnect are detected at the receiving node by performing a one bit parity check on the received status message using the accompanying parity code. Because the status message and the parity check code are transmitted over the same physical bit connections, the one bit parity checks detects any "stuck at" or "open" faults in the link.

2. 发明授权

US5987629A Interconnect fault detection and localization method and apparatus 失效
标题翻译：互连故障检测和定位方法及装置
公开(公告)号：US5987629A
公开(公告)日：1999-11-16
申请号：US45456
申请日：1998-03-20
申请人： Raghu Sastry , Jeffrey D. Larson , Albert Mu , John R. Slice , Richard L. Schober, Jr. , Thomas M. Wicki
发明人： Raghu Sastry , Jeffrey D. Larson , Albert Mu , John R. Slice , Richard L. Schober, Jr. , Thomas M. Wicki
IPC分类号： H04L1/00 , H04L1/08 , H04L1/24 , H04L12/26 , G06F11/00
CPC分类号： H04L1/0057 , H04L1/08 , H04L1/24 , H04L12/2697 , H04L43/50
摘要： A method and apparatus for detecting and isolating an interconnect fault in a packet switched network generates a parity check error code for status messages which are used for flow control in a packet switched network. The packet switched network uses a reverse flow control method wherein status messages are sent locally between adjacent nodes. A receiving node uses status messages to inform an adjacent node of the availability of the input buffers located in the receiving node. Included in the status message is a parity check code that is sent sequentially with the status message using two phases of a clock. The parity check code is a one bit parity check for each bit of the status message. Faults on the local interconnect are detected at the receiving node by performing a one bit parity check on the received status message using the accompanying parity code. Because the status message and the parity check code are transmitted over the same physical bit connections, the one bit parity checks detects any "stuck at" or "open" faults in the link.
摘要翻译：用于检测和隔离分组交换网络中的互连故障的方法和装置为分组交换网络中用于流量控制的状态消息生成奇偶校验错误代码。分组交换网络使用逆向流控制方法，其中状态消息在相邻节点之间本地发送。接收节点使用状态消息来向相邻节点通知位于接收节点中的输入缓冲器的可用性。包括在状态消息中的是奇偶校验码，该状态消息使用两个阶段的时钟与状态消息顺序发送。奇偶校验码是状态消息的每一位的一位奇偶校验。在接收节点通过使用伴随的奇偶校验码对接收到的状态消息执行一位奇偶校验来检测局部互连上的故障。由于状态消息和奇偶校验码通过相同的物理位连接传输，所以一位奇偶校验检测检测链路中的任何“卡住”或“打开”故障。

3. 发明授权

US06003064A System and method for controlling data transmission between network elements 失效
标题翻译：控制网元之间数据传输的系统和方法
公开(公告)号：US06003064A
公开(公告)日：1999-12-14
申请号：US603913
申请日：1996-02-22
申请人： Thomas M. Wicki , Patrick J. Helland , Jeffrey D. Larson , Albert Mu , Raghu Sastry , Richard L. Schober, Jr.
发明人： Thomas M. Wicki , Patrick J. Helland , Jeffrey D. Larson , Albert Mu , Raghu Sastry , Richard L. Schober, Jr.
IPC分类号： H04L29/08 , H04L12/56 , H04L13/08 , G06F13/12 , G06F13/14
CPC分类号： H04L47/30 , H04L47/10 , H04L47/26
摘要： A system and method for controlling data transmission between two network elements. A first port of a transmitting element is coupled to a second port of a receiving element. The second port includes buffers for temporarily storing received data until the data can be sent to another element. Included in the transmitting element are a received-currently-full register (RCFR), a sent-and-not-received register (SANRR), and a buffer-busy register (BBR). The transmitting element checks its BBR to determine if a buffer in the receiving element is available. The availability of buffers can be determined using a single priority protocol or a multiple priority protocol. If a buffer is available, the transmitting element transmits a data frame to the receiving element and sets the SANRR and the BBR to indicate that a frame has been sent (and that no acknowledgment has been received), that the selected buffer in the receiver is full, and that no additional data frames are to be sent to this buffer until the buffer is empty. When data is received by the receiving element, it is sent to an available buffer. When the data is received by the buffer, the receiving element sets a bit in a currently-full register (CFR) and a bit in a next-message-to-send register (NMTSR). A control signal is transmitted by the data receiving element on the same signal line as data that is being sent from the data receiving element to the data transmitting element. The data receiving element can multiplex the frames being sent in this direction with the control signal. When the transmitting element receives the control signal, it resets a bit associated with a buffer in the SANRR if the bit is set in the SANRR and if the associated bit in the NMTSR portion of the control signal is set.
摘要翻译：一种用于控制两个网络元件之间的数据传输的系统和方法。发射元件的第一端口耦合到接收元件的第二端口。第二端口包括用于临时存储接收到的数据的缓冲器，直到可以将数据发送到另一个元件。包含在发送元件中的是接收当前完整寄存器（RCFR），发送 - 未接收寄存器（SANRR）和缓冲器 - 忙寄存器（BBR）。发送元件检查其BBR以确定接收元件中的缓冲区是否可用。可以使用单一优先级协议或多优先级协议来确定缓冲区的可用性。如果缓冲器可用，则发送元件向接收元件发送数据帧，并将SANRR和BBR设置为指示已经发送了帧（并且没有接收到确认），接收器中所选择的缓冲器是完全，并且在缓冲区为空之前，不会将其他数据帧发送到此缓冲区。当接收元件接收到数据时，它被发送到可用的缓冲器。当数据被缓冲器接收时，接收单元设置当前完整寄存器（CFR）中的位和下一个消息发送寄存器（NMTSR）中的位。控制信号由数据接收元件在与数据接收元件发送到数据发送元件的数据相同的信号线上发送。数据接收元件可以将在该方向上发送的帧与控制信号进行复用。当发送元件接收到控制信号时，如果在SANRR中设置该位，并且控制信号的NMTSR部分中的关联位被置位，则复位与SANRR中的缓冲器有关的位。

4. 发明授权

US5838684A Low latency, high clock frequency plesioasynchronous packet-based crossbar switching chip system and method 失效
标题翻译：低延迟，高时钟频率同步分组交叉开关芯片系统和方法
公开(公告)号：US5838684A
公开(公告)日：1998-11-17
申请号：US603926
申请日：1996-02-22
申请人： Thomas M. Wicki , Jeffrey D. Larson , Albert Mu , Raghu Sastry
发明人： Thomas M. Wicki , Jeffrey D. Larson , Albert Mu , Raghu Sastry
IPC分类号： H04L12/56
CPC分类号： H04L49/253 , H04L49/101 , H04L49/1546 , H04L49/254 , H04L49/3018
摘要： An plesioasynchronous and asynchronous router circuit communicates with neighboring router circuits and nodes. Each of the router circuits includes a plurality of input ports for receiving frames of data and a plurality of output ports for transmitting frames of data. Each router circuit further includes a plurality of input buffers for storing frames of data received at an input port, and an arbiter system for choosing one of several input buffers associated with a particular one of said output ports. The arbiter system includes a plurality of arbiter subsystems associated with corresponding ones of said plurality of output ports. The plesioasynchronous and asynchronous router circuit further includes a crossbar switch for connecting an arbiter selected input buffer with a particular one of said output ports.
摘要翻译：异步和异步路由器电路与相邻的路由器电路和节点进行通信。每个路由器电路包括用于接收数据帧的多个输入端口和用于发送数据帧的多个输出端口。每个路由器电路还包括用于存储在输入端口处接收的数据帧的多个输入缓冲器和用于选择与特定一个所述输出端口相关联的多个输入缓冲器之一的仲裁器系统。仲裁器系统包括与所述多个输出端口中的相应的输出端口相关联的多个仲裁器子系统。同步和异步路由器电路还包括用于将仲裁器选择的输入缓冲器与特定的所述输出端口连接的交叉开关。

5. 发明授权

US06898742B2 System and method for automatic deskew across a high speed, parallel interconnection 失效
标题翻译：用于跨高速并行互连的自动校正的系统和方法
公开(公告)号：US06898742B2
公开(公告)日：2005-05-24
申请号：US10300389
申请日：2002-11-19
申请人： Yoichi Koyanagi , Richard L. Schober, Jr. , Raghu Sastry , Hirotaka Tamura
发明人： Yoichi Koyanagi , Richard L. Schober, Jr. , Raghu Sastry , Hirotaka Tamura
IPC分类号： G06F1/10 , G06F5/06 , H03K5/13 , H04L25/14 , G06K5/04
CPC分类号： G06F5/06 , H04L25/14
摘要： A method and system performs automatic deskew tuning and alignment across high-speed, parallel interconnections in a high performance digital system to compensate for inter-bit skew. Rather than using a VDL, digital elements such as registers and multiplexers are used for performing the automatic deskew tuning and alignment procedure. The result is a simpler, more robust deskew system capable of operating over a wider range of input values with greater accuracy and over a broader range of temperatures. In addition, the method and apparatus performs a one to four unfolding of the signal on each interconnection. The system includes a deskew controller and a plurality of deskew subsystems. The deskew controller automatically computes the amount of delay needed to correct the skew on each interconnection and feeds a different (or appropriate) delay value to each deskew subsystem located at the receiving end of each interconnection.
摘要翻译：一种方法和系统在高性能数字系统的高速，并行互连中进行自动偏移校正和对准，以补偿位间偏移。使用数字元件（如寄存器和多路复用器）而不是使用VDL来执行自动偏移校正和校准过程。结果是一个更简单，更强大的偏移校正系统，能够在更广泛的输入值范围内运行，具有更高的精度和更宽的温度范围。此外，该方法和装置在每个互连上执行一至四次的信号展开。该系统包括一个歪斜控制器和多个偏斜校正子系统。歪斜控制器自动计算纠正每个互连歪斜所需的延迟量，并将不同（或适当的）延迟值馈送到位于每个互连接收端的每个歪斜校正子系统。

6. 发明申请

US20110320252A1 Apparatus and Method for Redeeming an Incentive on a Wireless Device 审中-公开
标题翻译：在无线设备上兑换激励的设备和方法
公开(公告)号：US20110320252A1
公开(公告)日：2011-12-29
申请号：US13168898
申请日：2011-06-24
申请人： Raghu Sastry , Jae Kim , Christopher J. Sweis
发明人： Raghu Sastry , Jae Kim , Christopher J. Sweis
IPC分类号： G06Q30/00
CPC分类号： G06Q30/02 , G06Q30/0222
摘要： A non-transitory computer readable storage medium includes executable instructions to collect a first wireless internet protocol address associated with a wireless client device that initiates an invoked offer. The first wireless internet protocol address is associated with incentive identification information corresponding to the invoked offer. An application invocation page is delivered to the wireless client device. Log in information is received from the wireless client device. A second wireless internet protocol address accompanying the log in information is collected. The incentive identification information is retrieved if the first wireless internet protocol address matches the second internet protocol address. An incentive specified by the incentive identification information is then downloaded to the wireless client device.
摘要翻译：非暂时计算机可读存储介质包括可执行指令，用于收集与启动被引用报价的无线客户端设备相关联的第一无线因特网协议地址。第一无线互联网协议地址与激活的报价相对应的激励识别信息相关联。应用程序调用页面被传送到无线客户端设备。从无线客户端设备接收登录信息。收集伴随登录信息的第二个无线互联网协议地址。如果第一无线互联网协议地址与第二网际协议地址匹配，则检索激励识别信息。然后将激励识别信息指定的激励下载到无线客户端设备。

7. 发明授权

US06493320B1 Automatic initialization and tuning across a high speed, plesiochronous, parallel link 有权
标题翻译：通过高速，同步，并行链路自动初始化和调整
公开(公告)号：US06493320B1
公开(公告)日：2002-12-10
申请号：US09249825
申请日：1999-02-12
申请人： Richard L. Schober , Yoichi Koyanagi , Raghu Sastry , Hirotaka Tamura , Kohtaro Gotoh
发明人： Richard L. Schober , Yoichi Koyanagi , Raghu Sastry , Hirotaka Tamura , Kohtaro Gotoh
IPC分类号： G01R3108
CPC分类号： H04B17/0085
摘要： A method and apparatus automatically initialize and tune a link in a network system. The link couples one router to another router and may be implemented as a high speed, plesiochronous, parallel link. The apparatus includes a first link control unit coupled to a first end of the link and a second link control unit coupled to a second end of the link. The second link control unit is capable of communicating with the first link control unit to achieve automatic adjustment of the operating parameters of the link to maximize signal propagation across and minimize the power consumption of the link. The method of initializing and tuning across a high speed link in a network is also disclosed.
摘要翻译：方法和装置自动初始化和调整网络系统中的链路。该链路将一个路由器耦合到另一个路由器，并且可以被实现为高速，同步，并行链路。该装置包括耦合到链路的第一端的第一链路控制单元和耦合到链路的第二端的第二链路控制单元。第二链路控制单元能够与第一链路控制单元进行通信，以实现链路的操作参数的自动调整，以最大化跨越的信号传播并使链路的功率消耗最小化。还公开了通过网络中的高速链路进行初始化和调谐的方法。

8. 发明授权

US5535292A VLSI architectures for polygon recognition 失效
标题翻译：用于多边形识别的VLSI架构
公开(公告)号：US5535292A
公开(公告)日：1996-07-09
申请号：US174302
申请日：1993-12-30
申请人： Nagarajan Ranganathan , Raghu Sastry
发明人： Nagarajan Ranganathan , Raghu Sastry
IPC分类号： G06K9/64 , G06K9/54 , G06K9/60
CPC分类号： G06K9/6203 , G06K9/6211
摘要： A VLSI structure and method for polygon recognition that identifies an unknown two dimensional contour as corresponding to one or more of a plurality of known two dimensional contours. The VLSI architecture comprises a systolic processing system comprising a plurality of matrix element processing elements (MEPEs), and an array of feasible match processing elements (FMPEs) interconnected with selected MEPEs and with each other in a predetermined configuration. The plurality of MEPEs receive inputs comprising pairs of edge length ratios and corresponding threshold values for consecutive edges of the unknown contour and for each of the known polygon contours. Each MEPE (i) receives edge length ratios and threshold values for a pair of edges of the unknown contour and a known polygon contour, (ii) determines a dissimilarity value for the pair of edges, and (iii) directs this value to a selected FMPE of the array. The dissimilarity value is determined using the absolute differences between respective edge length ratios and threshold values for the pair of edges. The array of FMPEs determines feasible matches between pairs of consecutive edges of the unknown contour and the known polygon contours and delivers outputs related thereto, and a comparator device compares such outputs and delivers a final output which is indicative of the longest number of consecutive edges, above a predetermined minimum, for which feasible matches have occurred between the unknown contour and a known polygon contour.
摘要翻译：一种用于多边形识别的VLSI结构和方法，其将未知二维轮廓识别为对应于多个已知二维轮廓中的一个或多个。 VLSI架构包括包括多个矩阵元素处理元件（MEPE）的收缩处理系统以及与所选MEPE互连并且以预定配置彼此互连的可行匹配处理元件（FMPE）阵列。多个MEPE接收包括未知轮廓的连续边缘和已知多边形轮廓中的每一个的边缘长度比对和相应阈值对的输入。每个MEPE（i）接收未知轮廓的一对边缘和已知多边形轮廓的边缘长度比和阈值，（ii）确定该对边缘的不相似性值，以及（iii）将该值指向所选择的数组的FMPE。使用相应边缘长度比和该对边缘的阈值之间的绝对差确定不相似度值。 FMPE阵列确定了未知轮廓和已知多边形轮廓的连续边缘对之间的可行匹配，并且传送与之相关的输出，并且比较器装置比较这样的输出并递送表示最长连续边缘数的最终输出，高于预定最小值，在未知轮廓和已知多边形轮廓之间发生了可行的匹配。

9. 发明授权

US06636993B1 System and method for automatic deskew across a high speed, parallel interconnection 有权
标题翻译：用于跨高速并行互连的自动校正的系统和方法
公开(公告)号：US06636993B1
公开(公告)日：2003-10-21
申请号：US09249935
申请日：1999-02-12
申请人： Yoichi Koyanagi , Richard L. Schober , Raghu Sastry , Hirotaka Tamura
发明人： Yoichi Koyanagi , Richard L. Schober , Raghu Sastry , Hirotaka Tamura
IPC分类号： G06K504
CPC分类号： G06F5/06 , H04L25/14
摘要： A method and system performs automatic deskew tuning and alignment across high-speed, parallel interconnections in a high performance digital system to compensate for inter-bit skew. Rather than using a VDL, digital elements such as registers and multiplexers are used for performing the automatic deskew tuning and alignment procedure. The result is a simpler, more robust deskew system capable of operating over a wider range of input values with greater accuracy and over a broader range of temperatures. In addition, the method and apparatus performs a one to four unfolding of the signal on each interconnection. The system includes a deskew controller and a plurality deskew subsystems. The deskew controller computes the amount of delay needed to correct the skew on each interconnection and feeds a different (or appropriate) delay value to each deskew subsystem located at the receiving end of each interconnection.
摘要翻译：一种方法和系统在高性能数字系统的高速，并行互连中进行自动偏移校正和对准，以补偿位间偏移。使用数字元件（如寄存器和多路复用器）而不是使用VDL来执行自动偏移校正和校准过程。结果是一个更简单，更强大的偏移校正系统，能够在更广泛的输入值范围内运行，具有更高的精度和更宽的温度范围。此外，该方法和装置在每个互连上执行一至四次的信号展开。该系统包括一个歪斜控制器和多个歪斜系统子系统。歪斜控制器计算校正每个互连件上的偏斜所需的延迟量，并将不同（或适当的）延迟值馈送到位于每个互连接收端的每个歪斜校正子系统。

10. 发明授权

US5553272A VLSI circuit structure for determining the edit distance between strings 失效
标题翻译：用于确定字符串之间的编辑距离的VLSI电路结构
公开(公告)号：US5553272A
公开(公告)日：1996-09-03
申请号：US316320
申请日：1994-09-30
申请人： Nagarajan Ranganathan , Raghu Sastry
发明人： Nagarajan Ranganathan , Raghu Sastry
IPC分类号： G06F7/02 , G06K9/00 , G06F3/00 , G06F15/00
CPC分类号： G06K9/62 , G06F7/02 , G06K9/00973
摘要： The edit distance between two strings a.sub.1, . . . , a.sub.m and b.sub.1, . . . , b.sub.n is the minimum cost s of a sequence of editing operations (insertions, deletions and substitutions) that convert one string into the other. This invention provides VLSI circuit structure for computing the edit distance between two strings over a given alphabet. The circuit structure can perform approximate string matching for variable edit costs. More importantly, the circuit structure does not place any constraint on the lengths of the strings that can be compared. It makes use of simple basic cells and requires regular nearest-neighbor communication, which makes it suitable for VLSI implementation.
摘要翻译：两个字符串之间的编辑距离a1，。。。，am和b1，。。。，bn是将一个字符串转换为另一个字符串的编辑操作（插入，删除和替换）序列的最小成本。本发明提供了用于计算给定字母表上的两个字符串之间的编辑距离的VLSI电路结构。电路结构可以对可变编辑成本执行近似字符串匹配。更重要的是，电路结构对可以比较的串的长度没有任何约束。它使用简单的基本单元，并且需要定期的最近邻通信，这使得它适合于VLSI的实现。

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