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1. 发明授权

US06003064A System and method for controlling data transmission between network elements 失效
标题翻译：控制网元之间数据传输的系统和方法
公开(公告)号：US06003064A
公开(公告)日：1999-12-14
申请号：US603913
申请日：1996-02-22
申请人： Thomas M. Wicki , Patrick J. Helland , Jeffrey D. Larson , Albert Mu , Raghu Sastry , Richard L. Schober, Jr.
发明人： Thomas M. Wicki , Patrick J. Helland , Jeffrey D. Larson , Albert Mu , Raghu Sastry , Richard L. Schober, Jr.
IPC分类号： H04L29/08 , H04L12/56 , H04L13/08 , G06F13/12 , G06F13/14
CPC分类号： H04L47/30 , H04L47/10 , H04L47/26
摘要： A system and method for controlling data transmission between two network elements. A first port of a transmitting element is coupled to a second port of a receiving element. The second port includes buffers for temporarily storing received data until the data can be sent to another element. Included in the transmitting element are a received-currently-full register (RCFR), a sent-and-not-received register (SANRR), and a buffer-busy register (BBR). The transmitting element checks its BBR to determine if a buffer in the receiving element is available. The availability of buffers can be determined using a single priority protocol or a multiple priority protocol. If a buffer is available, the transmitting element transmits a data frame to the receiving element and sets the SANRR and the BBR to indicate that a frame has been sent (and that no acknowledgment has been received), that the selected buffer in the receiver is full, and that no additional data frames are to be sent to this buffer until the buffer is empty. When data is received by the receiving element, it is sent to an available buffer. When the data is received by the buffer, the receiving element sets a bit in a currently-full register (CFR) and a bit in a next-message-to-send register (NMTSR). A control signal is transmitted by the data receiving element on the same signal line as data that is being sent from the data receiving element to the data transmitting element. The data receiving element can multiplex the frames being sent in this direction with the control signal. When the transmitting element receives the control signal, it resets a bit associated with a buffer in the SANRR if the bit is set in the SANRR and if the associated bit in the NMTSR portion of the control signal is set.
摘要翻译：一种用于控制两个网络元件之间的数据传输的系统和方法。发射元件的第一端口耦合到接收元件的第二端口。第二端口包括用于临时存储接收到的数据的缓冲器，直到可以将数据发送到另一个元件。包含在发送元件中的是接收当前完整寄存器（RCFR），发送 - 未接收寄存器（SANRR）和缓冲器 - 忙寄存器（BBR）。发送元件检查其BBR以确定接收元件中的缓冲区是否可用。可以使用单一优先级协议或多优先级协议来确定缓冲区的可用性。如果缓冲器可用，则发送元件向接收元件发送数据帧，并将SANRR和BBR设置为指示已经发送了帧（并且没有接收到确认），接收器中所选择的缓冲器是完全，并且在缓冲区为空之前，不会将其他数据帧发送到此缓冲区。当接收元件接收到数据时，它被发送到可用的缓冲器。当数据被缓冲器接收时，接收单元设置当前完整寄存器（CFR）中的位和下一个消息发送寄存器（NMTSR）中的位。控制信号由数据接收元件在与数据接收元件发送到数据发送元件的数据相同的信号线上发送。数据接收元件可以将在该方向上发送的帧与控制信号进行复用。当发送元件接收到控制信号时，如果在SANRR中设置该位，并且控制信号的NMTSR部分中的关联位被置位，则复位与SANRR中的缓冲器有关的位。

2. 发明授权

US5987629A Interconnect fault detection and localization method and apparatus 失效
标题翻译：互连故障检测和定位方法及装置
公开(公告)号：US5987629A
公开(公告)日：1999-11-16
申请号：US45456
申请日：1998-03-20
申请人： Raghu Sastry , Jeffrey D. Larson , Albert Mu , John R. Slice , Richard L. Schober, Jr. , Thomas M. Wicki
发明人： Raghu Sastry , Jeffrey D. Larson , Albert Mu , John R. Slice , Richard L. Schober, Jr. , Thomas M. Wicki
IPC分类号： H04L1/00 , H04L1/08 , H04L1/24 , H04L12/26 , G06F11/00
CPC分类号： H04L1/0057 , H04L1/08 , H04L1/24 , H04L12/2697 , H04L43/50
摘要： A method and apparatus for detecting and isolating an interconnect fault in a packet switched network generates a parity check error code for status messages which are used for flow control in a packet switched network. The packet switched network uses a reverse flow control method wherein status messages are sent locally between adjacent nodes. A receiving node uses status messages to inform an adjacent node of the availability of the input buffers located in the receiving node. Included in the status message is a parity check code that is sent sequentially with the status message using two phases of a clock. The parity check code is a one bit parity check for each bit of the status message. Faults on the local interconnect are detected at the receiving node by performing a one bit parity check on the received status message using the accompanying parity code. Because the status message and the parity check code are transmitted over the same physical bit connections, the one bit parity checks detects any "stuck at" or "open" faults in the link.
摘要翻译：用于检测和隔离分组交换网络中的互连故障的方法和装置为分组交换网络中用于流量控制的状态消息生成奇偶校验错误代码。分组交换网络使用逆向流控制方法，其中状态消息在相邻节点之间本地发送。接收节点使用状态消息来向相邻节点通知位于接收节点中的输入缓冲器的可用性。包括在状态消息中的是奇偶校验码，该状态消息使用两个阶段的时钟与状态消息顺序发送。奇偶校验码是状态消息的每一位的一位奇偶校验。在接收节点通过使用伴随的奇偶校验码对接收到的状态消息执行一位奇偶校验来检测局部互连上的故障。由于状态消息和奇偶校验码通过相同的物理位连接传输，所以一位奇偶校验检测检测链路中的任何“卡住”或“打开”故障。

3. 发明授权

US5768300A Interconnect fault detection and localization method and apparatus 失效
公开(公告)号：US5768300A
公开(公告)日：1998-06-16
申请号：US603911
申请日：1996-02-22
申请人： Raghu Sastry , Jeffrey D. Larson , Albert Mu , John R. Slice , Richard L. Schober, Jr. , Thomas M. Wicki
发明人： Raghu Sastry , Jeffrey D. Larson , Albert Mu , John R. Slice , Richard L. Schober, Jr. , Thomas M. Wicki
IPC分类号： H04L1/00 , H04L1/08 , H04L1/24 , H04L12/26 , G06F11/10 , H03M13/00
CPC分类号： H04L1/0057 , H04L1/08 , H04L1/24 , H04L12/2697 , H04L43/50
摘要： A method and apparatus for detecting and isolating an interconnect fault in a packet switched network generates a parity check error code for status messages which are used for flow control in a packet switched network. The packet switched network uses a reverse flow control method wherein status messages are sent locally between adjacent nodes. A receiving node uses status messages to inform an adjacent node of the availability of the input buffers located in the receiving node. Included in the status message is a parity check code that is sent sequentially with the status message using two phases of a clock. The parity check code is a one bit parity check for each bit of the status message. Faults on the local interconnect are detected at the receiving node by performing a one bit parity check on the received status message using the accompanying parity code. Because the status message and the parity check code are transmitted over the same physical bit connections, the one bit parity checks detects any "stuck at" or "open" faults in the link.

4. 发明授权

US06898742B2 System and method for automatic deskew across a high speed, parallel interconnection 失效
标题翻译：用于跨高速并行互连的自动校正的系统和方法
公开(公告)号：US06898742B2
公开(公告)日：2005-05-24
申请号：US10300389
申请日：2002-11-19
申请人： Yoichi Koyanagi , Richard L. Schober, Jr. , Raghu Sastry , Hirotaka Tamura
发明人： Yoichi Koyanagi , Richard L. Schober, Jr. , Raghu Sastry , Hirotaka Tamura
IPC分类号： G06F1/10 , G06F5/06 , H03K5/13 , H04L25/14 , G06K5/04
CPC分类号： G06F5/06 , H04L25/14
摘要： A method and system performs automatic deskew tuning and alignment across high-speed, parallel interconnections in a high performance digital system to compensate for inter-bit skew. Rather than using a VDL, digital elements such as registers and multiplexers are used for performing the automatic deskew tuning and alignment procedure. The result is a simpler, more robust deskew system capable of operating over a wider range of input values with greater accuracy and over a broader range of temperatures. In addition, the method and apparatus performs a one to four unfolding of the signal on each interconnection. The system includes a deskew controller and a plurality of deskew subsystems. The deskew controller automatically computes the amount of delay needed to correct the skew on each interconnection and feeds a different (or appropriate) delay value to each deskew subsystem located at the receiving end of each interconnection.
摘要翻译：一种方法和系统在高性能数字系统的高速，并行互连中进行自动偏移校正和对准，以补偿位间偏移。使用数字元件（如寄存器和多路复用器）而不是使用VDL来执行自动偏移校正和校准过程。结果是一个更简单，更强大的偏移校正系统，能够在更广泛的输入值范围内运行，具有更高的精度和更宽的温度范围。此外，该方法和装置在每个互连上执行一至四次的信号展开。该系统包括一个歪斜控制器和多个偏斜校正子系统。歪斜控制器自动计算纠正每个互连歪斜所需的延迟量，并将不同（或适当的）延迟值馈送到位于每个互连接收端的每个歪斜校正子系统。

5. 发明授权

US08726124B2 Cyclic redundancy check generation via distributed time multiplexed linear feedback shift registers 有权
标题翻译：通过分布式时间复用线性反馈移位寄存器生成循环冗余校验
公开(公告)号：US08726124B2
公开(公告)日：2014-05-13
申请号：US13553583
申请日：2012-07-19
申请人： Eric Lyell Hill , Richard L. Schober, Jr. , Hungse Cha
发明人： Eric Lyell Hill , Richard L. Schober, Jr. , Hungse Cha
IPC分类号： H03M13/00
CPC分类号： G06F11/1004 , H03M13/091 , H03M13/6502 , H03M13/6575
摘要： Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.
摘要翻译：使用改进的线性反馈移位寄存器（LFSR）电路有效地计算循环冗余校验（CRC）值。 CRC值生成被分成两个子计算，然后将它们组合以形成最终的CRC值。可编程XOR引擎通过表查找执行逻辑功能，而不是通过随机逻辑电路执行逻辑功能。使用单个共享LFSR电路执行LCRC和ECRC计算。多个链路共享相同的CRC值生成器。本发明的一个优点是使用相对于常规电路设计的较小和较少的LFSR电路产生CRC值。结果，利用所公开的技术的CRC值发生器消耗了较少的集成电路的表面积并且消耗较少的功率，导致较冷的操作。

6. 发明授权

US08738990B2 Cyclic redundancy check generation via distributed time multiplexed linear feedback shift registers 有权
公开(公告)号：US08738990B2
公开(公告)日：2014-05-27
申请号：US13553619
申请日：2012-07-19
申请人： Eric Lyell Hill , Richard L. Schober, Jr. , Hungse Cha
发明人： Eric Lyell Hill , Richard L. Schober, Jr. , Hungse Cha
IPC分类号： H03M13/00
CPC分类号： H03M13/6502 , H03M13/091 , H03M13/6575 , H04L1/0061
摘要： Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.

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