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1. 发明授权

US06599830B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US06599830B2
公开(公告)日：2003-07-29
申请号：US10187998
申请日：2002-07-03
申请人： Takeshi Furusawa , Takao Kumihashi , Shuntaro Machida
发明人： Takeshi Furusawa , Takao Kumihashi , Shuntaro Machida
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/02126 , H01L21/02282 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/3122 , H01L21/76802 , H01L21/76807 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.

2. 发明授权

US06479380B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06479380B2
公开(公告)日：2002-11-12
申请号：US09863348
申请日：2001-05-24
申请人： Takeshi Furusawa , Takao Kumihashi , Shuntaro Machida
发明人： Takeshi Furusawa , Takao Kumihashi , Shuntaro Machida
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/02126 , H01L21/02282 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/3122 , H01L21/76802 , H01L21/76807 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.
摘要翻译：为了提供一种制造半导体器件的方法，通过该方法可以在具有低介电常数的甲基硅氧烷型膜上形成具有高纵横比的沟槽或孔，即使在较低的情况下也不会导致通孔连接故障或短路故障层间互连覆盖有蚀刻阻挡层。该方法包括在甲基硅氧烷型膜的上层上形成具有氧化硅膜的层状膜并使用硬掩模形成层叠膜的工序。当蚀刻阻挡层被蚀刻时，氧化硅膜用作甲基硅氧烷型膜的硬掩模，并且防止了向甲基硅氧烷型膜的转印。因此，可以减少多级互连的寄生电容，而不会导致通路连接故障和短路故障。

3. 发明授权

US06680541B2 Semiconductor device and process for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06680541B2
公开(公告)日：2004-01-20
申请号：US10050859
申请日：2002-01-18
申请人： Takeshi Furusawa , Daisuke Ryuzaki , Noriyuki Sakuma , Shuntaro Machida , Kenji Hinode , Ryou Yoneyama
发明人： Takeshi Furusawa , Daisuke Ryuzaki , Noriyuki Sakuma , Shuntaro Machida , Kenji Hinode , Ryou Yoneyama
IPC分类号： H01L23522
CPC分类号： H01L21/76808 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.
摘要翻译：至少含有硅原子，氧原子和碳原子的氧原子与硅原子的数量比为1.5以上，碳原子数与硅原子数之比为1〜2的金属间绝缘膜，具有膜厚收缩率在14％以下的氧化时，介电常数非常低，抗蚀剂蚀刻的选择性高，可以在半导体器件中不使用氧化硅保护膜的情况下使用。

4. 发明授权

US06358838B2 Semiconductor device and process for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06358838B2
公开(公告)日：2002-03-19
申请号：US09760777
申请日：2001-01-17
申请人： Takeshi Furusawa , Daisuke Ryuzaki , Noriyuki Sakuma , Shuntaro Machida , Kenji Hinode , Ryou Yoneyama
发明人： Takeshi Furusawa , Daisuke Ryuzaki , Noriyuki Sakuma , Shuntaro Machida , Kenji Hinode , Ryou Yoneyama
IPC分类号： H01L21311
CPC分类号： H01L21/76808 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.
摘要翻译：至少含有硅原子，氧原子和碳原子的氧原子与硅原子的数量比为1.5以上，碳原子数与硅原子数之比为1〜2的金属间绝缘膜，具有膜厚收缩率在14％以下的氧化时，介电常数非常低，抗蚀剂蚀刻的选择性高，可以在半导体器件中不使用氧化硅保护膜的情况下使用。

5. 发明授权

US08431420B2 Manufacturing method of ultrasonic probe and ultrasonic probe 失效
标题翻译：超声波探头和超声波探头的制造方法
公开(公告)号：US08431420B2
公开(公告)日：2013-04-30
申请号：US13144229
申请日：2010-01-06
申请人： Takashi Kobayashi , Shuntaro Machida
发明人： Takashi Kobayashi , Shuntaro Machida
IPC分类号： H01L21/66
CPC分类号： B06B1/0292
摘要： The manufacturing yield of semiconductor devices (CMUTs) is improved. Before a polyimide film serving as a protective film is formed, a membrane is repeatedly vibrated to evaluate the breakdown voltage between an upper electrode and a lower electrode, and the upper electrode of a defective CMUT cell whose breakdown voltage between the upper electrode and the lower electrode is reduced due to the repeated vibrations of the membrane is removed in advance to cut off the electrical connection with other normal CMUT cells. By this means, in a block RB or a channel RCH including the recovered CMUT cell RC, reduction in the breakdown voltage between the upper electrode and the lower electrode after the repeated vibrations of the membrane is prevented.
摘要翻译：改善了半导体器件（CMUT）的制造成品率。在形成用作保护膜的聚酰亚胺膜之前，膜被反复振动以评估上电极和下电极之间的击穿电压，以及上电极和下电极之间的击穿电压的缺陷CMUT电池的上电极由于膜的重复振动预先被去除以切断与其他正常CMUT电池的电连接，电极被还原。通过这种方式，在块RB或包括恢复的CMUT单元RC的通道RCH中，防止了在膜的重复振动之后上部电极和下部电极之间的击穿电压的降低。

6. 发明授权

US08132462B2 Ultrasonographic device 有权
标题翻译：超声波装置
公开(公告)号：US08132462B2
公开(公告)日：2012-03-13
申请号：US11996532
申请日：2006-01-30
申请人： Takashi Azuma , Shinichiro Umemura , Tatsuya Nagata , Hiroshi Fukuda , Shuntaro Machida , Toshiyuki Mine
发明人： Takashi Azuma , Shinichiro Umemura , Tatsuya Nagata , Hiroshi Fukuda , Shuntaro Machida , Toshiyuki Mine
IPC分类号： G01N29/34 , H02N1/08
CPC分类号： A61B8/4483 , A61B8/08 , A61B8/4281 , B06B1/0292 , G01N29/2431 , G01S15/00
摘要： The receive sensitivity of an ultrasound array transducer structured with a diaphragm electro-acoustic transducer (101) being a basic unit is affected by change in a charge amount with elapsed time due to leakage or the like, which causes drift of the primary beam sensitivity, degradation in the acoustic SN ratio due to a rise in the acoustic noise level, and degradation in the directivity of an ultrasound beam. To addressing this problem, a charge controller (charge monitor 211) is provided to control charge in an electro-acoustic transducer (101). A charge monitoring section (102) monitors the change in the charge amount. When change in the charge amount is small, transmit sensitivity or receive sensitivity is calibrated by a controller (104) by, for example, multiplying a receive signal by a calibration coefficient corresponding to the change amount. Further, when the change in the charge amount is large, for example, charges can be re-emitted from a charge emitter (103).
摘要翻译：由作为基本单元的隔膜电声换能器（101）构成的超声波阵列换能器的接收灵敏度受到由于泄漏等引起的经过时间的电荷量的变化的影响，导致主光束灵敏度的漂移，由于声学噪声水平的上升引起的声学SN比的降低，以及超声波束的方向性的劣化。为了解决这个问题，提供一种充电控制器（充电监视器211）来控制电声换能器（101）中的电荷。充电监视部（102）监视充电量的变化。当充电量的变化小时，通过例如将接收信号乘以对应于变化量的校准系数，由控制器（104）校准发射灵敏度或接收灵敏度。此外，当电荷量的变化大时，例如，电荷可以从电荷发射体（103）重新发射。

7. 发明申请

US20110086443A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110086443A1
公开(公告)日：2011-04-14
申请号：US12999478
申请日：2009-06-05
申请人： Takashi Kobayashi , Shuntaro Machida , Kunio Hashiba
发明人： Takashi Kobayashi , Shuntaro Machida , Kunio Hashiba
IPC分类号： H01L21/82 , H01L21/66
CPC分类号： H04R31/00 , B81B2201/0257 , B81B2207/053 , B81C1/00214
摘要： A manufacturing yield of a semiconductor device (capacitive micromachined ultrasonic transducer) is increased. A plurality of first chips 1 in which a plurality of cells each having functions of transmitting and receiving ultrasonic waves are formed on a front surface of a first semiconductor wafer are manufactured, and each of the first chips 1 is judged as a superior/inferior product, and then, the first semiconductor wafer is sigulated into a plurality of first chips 1. Next, a plurality of second chips 2 in which a wiring layer is formed on a front surface of a second semiconductor wafer are manufactured, and each of the second chips 2 is judged as a superior/inferior product, and then, the second semiconductor wafer is sigulated into a plurality of second chips 2. Next, the plurality of first chips 1 judged as the superior product are adjacently arranged on the front surface of the second chip 2 judged as the superior product in plane in a Y direction so that lower electrodes 5 of the adjacent first chips 1 are electrically connected with each other via a through electrode 6, a bump 8, and a wiring layer 7.
摘要翻译：半导体器件（电容式微加工超声换能器）的制造产量增加。制造在第一半导体晶片的前表面上形成多个具有发送和接收超声波功能的多个单元的多个第一芯片1，并且将第一芯片1判断为上/下产品然后，第一半导体晶片被配置成多个第一芯片1.接着，制造在第二半导体晶片的前表面上形成有布线层的多个第二芯片2，将芯片2判断为优劣产品，然后将第二半导体晶片投入多个第二芯片2.接下来，判断为优质产品的多个第一芯片1相邻布置在第二芯片2在Y方向上被认为是平面上的优异产品，使得相邻的第一芯片1的下电极5经由通电极6，凸块8和布线层7。

8. 发明授权

US07860258B2 Electro-acoustic transducer device 有权
标题翻译：电声换能器装置
公开(公告)号：US07860258B2
公开(公告)日：2010-12-28
申请号：US11491198
申请日：2006-07-24
申请人： Takashi Azuma , Shin-ichiro Umemura , Tatsuya Nagata , Hiroshi Fukuda , Shuntaro Machida , Toshiyuki Mine
发明人： Takashi Azuma , Shin-ichiro Umemura , Tatsuya Nagata , Hiroshi Fukuda , Shuntaro Machida , Toshiyuki Mine
IPC分类号： H04R25/00
CPC分类号： B06B1/0292 , H04R19/005
摘要： A transducer for transmitting and receiving ultrasonic waves to a diaphragm-based ultrasonic transducer device using silicon as a base material. An electro-acoustic transducer device which can have a first electrode formed on top of, or inside, a substrate and having a thin film provided on top of the substrate. The device can also have a second electrode formed on top of, or inside, the thin film. A void layer can be provided between the first electrode and the second electrode. A charge-storage layer can be provided between the first electrode and the second electrode. A source electrode and a drain electrode can also be provided for measuring a quantity of electricity stored in the charge-storage layer.
摘要翻译：一种用于将超声波发送和接收到使用硅作为基材的基于隔膜的超声波换能器装置的换能器。一种电声换能器装置，其可以具有形成在基板的顶部或内部并且具有设置在基板顶部上的薄膜的第一电极。该器件还可以具有形成在薄膜的顶部或内部的第二电极。可以在第一电极和第二电极之间设置空隙层。可以在第一电极和第二电极之间设置电荷存储层。还可以提供源电极和漏电极来测量存储在电荷存储层中的电量。

9. 发明授权

US07667374B2 Ultrasonic transducer, ultrasonic probe and method for fabricating the same 有权
标题翻译：超声波换能器，超声波探头及其制造方法
公开(公告)号：US07667374B2
公开(公告)日：2010-02-23
申请号：US11657186
申请日：2007-01-23
申请人： Takanori Aono , Tatsuya Nagata , Hiroyuki Enomoto , Shuntaro Machida
发明人： Takanori Aono , Tatsuya Nagata , Hiroyuki Enomoto , Shuntaro Machida
IPC分类号： H01L41/00
CPC分类号： B06B1/0292
摘要： In an ultrasonic transducer including a gap between an upper electrode and a lower electrode on a silicon substrate, it is made possible to reduce or adjust warpage of an above-gap membrane vibrated by electrostatic actuation due to internal stress. A fourth insulating film and a fifth insulating film of films positioned above the gap which is a cavity required for transmitting and receiving ultrasonic are respectively a silicon oxide film for compression stress and a silicon nitride film for tensile stress. Therefore, compression stress and tensile stress cancel each other, so that warpage of the above-gap membrane is reduced. An amount of warpage can be adjusted by adjusting a film thickness of the fourth insulating film and a film thickness of the fifth insulating film.
摘要翻译：在包括硅基板上的上电极和下电极之间的间隙的超声波换能器中，由于内部应力，能够减少或调整由静电驱动振动的上间隙膜的翘曲。位于间隙上方的膜的第四绝缘膜和第五绝缘膜分别是用于发送和接收超声波所需的腔，分别是用于压缩应力的氧化硅膜和用于拉伸应力的氮化硅膜。因此，压缩应力和拉伸应力彼此抵消，从而减小了上间隙膜的翘曲。可以通过调整第四绝缘膜的膜厚度和第五绝缘膜的膜厚来调节翘曲量。

10. 发明申请

US20080259733A1 ULTRASONIC TRANSDUCER AND MANUFACTURING METHOD THEREOF 有权
标题翻译：超声波传感器及其制造方法
公开(公告)号：US20080259733A1
公开(公告)日：2008-10-23
申请号：US11867681
申请日：2007-10-04
申请人： Shuntaro Machida , Hiroyuki Enomoto
发明人： Shuntaro Machida , Hiroyuki Enomoto
IPC分类号： B06B1/02
CPC分类号： B06B1/0292
摘要： A technology capable of improving receiver sensitivity and improving insulation withstand voltage in an ultrasonic transducer is provided. An ultrasonic transducer comprises: a lower electrode; an insulator covering the lower electrode; a cavity portion disposed on the insulator so as to overlap with the lower electrode; and an upper electrode disposed so as to overlap with the cavity portion. In this ultrasonic transducer, an insulator is inserted between the upper and lower electrodes in a part not having the cavity portion. By this means, sum total of thickness of insulators between the upper and lower electrodes in a part not having the cavity portion is larger than sum total of thickness of insulators between the upper and lower electrodes in a part having the cavity portion.
摘要翻译：提供了一种能够提高接收机灵敏度并提高超声波换能器中绝缘耐压的技术。超声换能器包括：下电极; 覆盖下电极的绝缘体; 空腔部分，设置在所述绝缘体上以与所述下电极重叠; 以及设置成与空腔部分重叠的上电极。在该超声波换能器中，在不具有空腔部的部分中，在上下电极之间插入绝缘体。通过这种方式，在不具有空腔部分的部分中的上部和下部电极之间的绝缘体的厚度的总和大于具有空腔部分的部分中的上部和下部电极之间的绝缘体的厚度的总和。

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