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1. 发明授权

US07586130B2 Vertical field effect transistor using linear structure as a channel region and method for fabricating the same 有权
标题翻译：使用线性结构作为沟道区域的垂直场效应晶体管及其制造方法
公开(公告)号：US07586130B2
公开(公告)日：2009-09-08
申请号：US11344574
申请日：2006-02-01
申请人： Takahiro Kawashima , Tohru Saitoh , Takeshi Takagi
发明人： Takahiro Kawashima , Tohru Saitoh , Takeshi Takagi
IPC分类号： H01L29/732
CPC分类号： H01L29/78696 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/1606 , H01L29/42384 , H01L29/7781 , H01L29/78642 , Y10S977/938
摘要： A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion sticking out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.
摘要翻译：垂直场效应晶体管包括：具有用作沟道区的线性结构束的有源区; 用作源极和漏极区之一的下电极; 上电极，用作源极和漏极区域中的另一个; 用于控制所述有源区域中包括的所述线性结构束的至少一部分的电导率的栅电极; 以及栅极绝缘膜，其布置在所述有源区和所述栅电极之间，以将所述栅电极与所述线结构的束电隔离。晶体管还包括在上电极和下电极之间的电介质部分。上电极位于下电极的上方，电介质部分插入，并且包括从电介质部分的上方横向突出的突出部分。有源区域位于上电极的伸出部分正下方。

2. 发明授权

US08486788B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08486788B2
公开(公告)日：2013-07-16
申请号：US13162310
申请日：2011-06-16
申请人： Junko Iwanaga , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
发明人： Junko Iwanaga , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.
摘要翻译：一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

3. 发明申请

US20060208300A1 Finfet-type semiconductor device and method for fabricating the same 有权
标题翻译： Finfet型半导体器件及其制造方法
公开(公告)号：US20060208300A1
公开(公告)日：2006-09-21
申请号：US10549291
申请日：2004-03-19
申请人： Junko Iwanaga , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
发明人： Junko Iwanaga , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
IPC分类号： H01L27/108
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.
摘要翻译：一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

4. 发明申请

US20110244645A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110244645A1
公开(公告)日：2011-10-06
申请号：US13162310
申请日：2011-06-16
申请人： Junko IWANAGA , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
发明人： Junko IWANAGA , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.
摘要翻译：一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

5. 发明授权

US07986002B2 FINFET-type semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07986002B2
公开(公告)日：2011-07-26
申请号：US10549291
申请日：2004-03-19
申请人： Junko Iwanaga , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
发明人： Junko Iwanaga , Takeshi Takagi , Yoshihiko Kanzawa , Haruyuki Sorada , Tohru Saitoh , Takahiro Kawashima
IPC分类号： H01L29/66
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.
摘要翻译：一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

6. 发明申请

US20060125025A1 Vertical field effect transistor and method for fabricating the same 有权
标题翻译：垂直场效应晶体管及其制造方法
公开(公告)号：US20060125025A1
公开(公告)日：2006-06-15
申请号：US11344574
申请日：2006-02-01
申请人： Takahiro Kawashima , Tohru Saitoh , Takeshi Takagi
发明人： Takahiro Kawashima , Tohru Saitoh , Takeshi Takagi
IPC分类号： H01L29/76
CPC分类号： H01L29/78696 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/1606 , H01L29/42384 , H01L29/7781 , H01L29/78642 , Y10S977/938
摘要： A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region where electric carriers are transported; a lower electrode, connected to the bottom of the active region and functioning as one of source and drain regions; an upper electrode, connected to the top of the active region and functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion that sticks out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.
摘要翻译：垂直场效应晶体管包括：有源区，其具有用作传输电载体的沟道区的线性结构束; 下电极，连接到有源区的底部并用作源极和漏极区之一; 上电极，连接到有源区的顶部并用作源极和漏极区域中的另一个; 用于控制所述有源区域中包括的所述线性结构束的至少一部分的电导率的栅电极; 以及栅极绝缘膜，其布置在所述有源区和所述栅电极之间，以将所述栅电极与所述线结构的束电隔离。晶体管还包括在上电极和下电极之间的电介质部分。上电极位于下电极的上方，电介质部分插入，并且包括从电介质部分的上方向外伸出的突出部分。有源区域位于上电极的伸出部分正下方。

7. 发明授权

US06852602B2 Semiconductor crystal film and method for preparation thereof 失效
标题翻译：半导体晶体膜及其制备方法
公开(公告)号：US06852602B2
公开(公告)日：2005-02-08
申请号：US10298000
申请日：2002-01-30
申请人： Yoshihiko Kanzawa , Tohru Saitoh , Katsuya Nozawa , Minoru Kubo , Yoshihiro Hara , Takeshi Takagi , Takahiro Kawashima
发明人： Yoshihiko Kanzawa , Tohru Saitoh , Katsuya Nozawa , Minoru Kubo , Yoshihiro Hara , Takeshi Takagi , Takahiro Kawashima
IPC分类号： H01L21/205 , H01L29/15 , H01L29/24 , H01L29/737 , H01L29/80 , H01L21/331
CPC分类号： H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02505 , H01L21/02507 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02661 , H01L29/155 , H01L29/1608 , H01L29/7378 , H01L29/802
摘要： A multi-layer film 10 is formed by stacking a Si1-x1-y1Gex1Cy1 layer (0≦x1 y2) having a high Ge mole fraction, e.g., a Si0.2Ge0.8 layer 12. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.
摘要翻译：通过层叠具有小Ge摩尔分数的Si1-x1-y1Gex1Cy1层（0 <= x1 <1和0 y2），例如Si0.2Ge0.8层以这种方式，多层膜用作结合到晶格点中的C原子的SiGeC层的范围延伸到Ge摩尔分数高的高度。

8. 发明授权

US06858454B1 Method for measuring semiconductor constituent element content and method for manufacturing a semiconductor device 有权
标题翻译：用于测量半导体构成元件含量的方法和用于制造半导体器件的方法
公开(公告)号：US06858454B1
公开(公告)日：2005-02-22
申请号：US10674523
申请日：2003-10-01
申请人： Yoshihiko Kanzawa , Tohru Saitoh , Takeshi Takagi , Katsuya Nozawa
发明人： Yoshihiko Kanzawa , Tohru Saitoh , Takeshi Takagi , Katsuya Nozawa
IPC分类号： G01N21/21 , G01N21/35 , H01L21/66
CPC分类号： G01N21/3563 , G01N21/211
摘要： A method for measuring semiconductor constituent element content utilizes the steps of: obtaining a film thickness of an SiGeC layer formed on a semiconductor substrate by evaluation using spectroscopic ellipsometry; measuring infrared absorption spectrum of the SiGeC layer; and obtaining a C content of the SiGeC layer based on the film thickness and the infrared absorption spectrum of the SiGeC layer. The method: obtaining an apparent Ge content of the SiGeC layer by evaluation using spectroscopic ellipsometry; and obtaining an actual Ge content of the SiGeC layer based on the apparent Ge content and the C content. The constituent element content of the SiGeC layer can be easily and accurately measured according to the above-mentioned method.
摘要翻译：一种测量半导体构成元件含量的方法采用以下步骤：通过使用分光椭圆偏光度法评估在半导体衬底上形成的SiGeC层的膜厚度; 测量SiGeC层的红外吸收光谱; 并根据SiGeC层的膜厚和红外吸收光谱获得SiGeC层的C含量。该方法：通过使用分光椭偏仪评估获得SiGeC层的表观Ge含量; 并且基于表观Ge含量和C含量获得SiGeC层的实际Ge含量。根据上述方法可以容易且精确地测量SiGeC层的构成元素含量。

9. 发明授权

US06399993B1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06399993B1
公开(公告)日：2002-06-04
申请号：US09786551
申请日：2001-03-07
申请人： Teruhito Ohnishi , Akira Asai , Takeshi Takagi , Tohru Saitoh , Yo Ichikawa , Yoshihiro Hara , Koichiro Yuki , Katsuya Nozawa , Koji Katayama , Yoshihiko Kanzawa
发明人： Teruhito Ohnishi , Akira Asai , Takeshi Takagi , Tohru Saitoh , Yo Ichikawa , Yoshihiro Hara , Koichiro Yuki , Katsuya Nozawa , Koji Katayama , Yoshihiko Kanzawa
IPC分类号： H01L2972
CPC分类号： H01L21/76237 , H01L21/8249
摘要： In a bipolar transistor block, a base layer (20a) of SiGe single crystals and an emitter layer (26) of almost 100% of Si single crystals are stacked in this order over a collector diffused layer (9). Over both edges of the base layer (20a), a base undercoat insulating film (5a) and base extended electrodes (22) made of polysilicon are provided. The base layer (20a) has a peripheral portion with a thickness equal to that of the base undercoat insulating film (5a) and a center portion thicker than the peripheral portion. The base undercoat insulating film (5a) and gate insulating films (5b and 5c) for a CMOS block are made of the same oxide film. A stress resulting from a difference in thermal expansion coefficient between the SiGe layer as the base layer and the base undercoat insulating film 5a can be reduced, and a highly reliable BiCMOS device is realized.
摘要翻译：在双极晶体管块中，SiGe单晶的基极层（20a）和几乎100％的Si单晶的发射极层（26）依次层叠在集电极扩散层（9）上。在基底层（20a）的两个边缘上设置有由多晶硅制成的基底底涂层绝缘膜（5a）和基底延伸电极（22）。基底层（20a）具有与基底底涂层绝缘膜（5a）的厚度相等的周边部分和比周边部分厚的中心部分。用于CMOS块的基底涂层绝缘膜（5a）和栅极绝缘膜（5b和5c）由相同的氧化物膜制成。由于作为基底层的SiGe层与基底底涂层绝缘膜5a之间的热膨胀系数的差异导致的应力可以降低，并且实现了高可靠性的BiCMOS器件。

10. 发明授权

US06713790B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06713790B2
公开(公告)日：2004-03-30
申请号：US10212799
申请日：2002-08-07
申请人： Akira Asai , Teruhito Oonishi , Takeshi Takagi , Tohru Saitoh , Yoshihiro Hara , Koichiro Yuki , Katsuya Nozawa , Yoshihiko Kanzawa , Koji Katayama , Yo Ichikawa
发明人： Akira Asai , Teruhito Oonishi , Takeshi Takagi , Tohru Saitoh , Yoshihiro Hara , Koichiro Yuki , Katsuya Nozawa , Yoshihiko Kanzawa , Koji Katayama , Yo Ichikawa
IPC分类号： H01L31072
CPC分类号： H01L29/66242 , H01L21/763 , H01L21/8249 , H01L27/0623 , H01L29/7378
摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.
摘要翻译：在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极层。通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电极开口的范围覆盖集电极层和器件隔离的一部分。在位于集电体开口内部的半导体基板的一部分上形成作为外部基底的第二导电类型的半导体层，同时在半导体衬底中形成与外部基底相同的导电类型的防漏层。因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

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