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1. 发明授权

US06455364B1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06455364B1
公开(公告)日：2002-09-24
申请号：US09526686
申请日：2000-03-15
申请人： Akira Asai , Teruhito Oonishi , Takeshi Takagi , Tohru Saitoh , Yoshihiro Hara , Koichiro Yuki , Katsuya Nozawa , Yoshihiko Kanzawa , Koji Katayama , Yo Ichikawa
发明人： Akira Asai , Teruhito Oonishi , Takeshi Takagi , Tohru Saitoh , Yoshihiro Hara , Koichiro Yuki , Katsuya Nozawa , Yoshihiko Kanzawa , Koji Katayama , Yo Ichikawa
IPC分类号： H01L218249
CPC分类号： H01L29/66242 , H01L21/763 , H01L21/8249 , H01L27/0623 , H01L29/7378
摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.
摘要翻译：在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极层。通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电极开口的范围覆盖集电极层和器件隔离的一部分。在位于集电体开口内部的半导体基板的一部分上形成作为外部基底的第二导电类型的半导体层，同时在半导体衬底中形成与外部基底相同的导电类型的防漏层。因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

2. 发明授权

US06713790B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06713790B2
公开(公告)日：2004-03-30
申请号：US10212799
申请日：2002-08-07
申请人： Akira Asai , Teruhito Oonishi , Takeshi Takagi , Tohru Saitoh , Yoshihiro Hara , Koichiro Yuki , Katsuya Nozawa , Yoshihiko Kanzawa , Koji Katayama , Yo Ichikawa
发明人： Akira Asai , Teruhito Oonishi , Takeshi Takagi , Tohru Saitoh , Yoshihiro Hara , Koichiro Yuki , Katsuya Nozawa , Yoshihiko Kanzawa , Koji Katayama , Yo Ichikawa
IPC分类号： H01L31072
CPC分类号： H01L29/66242 , H01L21/763 , H01L21/8249 , H01L27/0623 , H01L29/7378
摘要： In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.
摘要翻译：在本发明的半导体装置的制造方法中，在被器件分离夹持的半导体基板的区域中形成有第一导电型的集电极层。通过沉积在半导体衬底上的第一绝缘层形成集电极开口，使得集电极开口的范围覆盖集电极层和器件隔离的一部分。在位于集电体开口内部的半导体基板的一部分上形成作为外部基底的第二导电类型的半导体层，同时在半导体衬底中形成与外部基底相同的导电类型的防漏层。因此，有源区域比集电极开口窄，减小晶体管面积，同时最小化结漏电。

3. 发明授权

US06399993B1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06399993B1
公开(公告)日：2002-06-04
申请号：US09786551
申请日：2001-03-07
申请人： Teruhito Ohnishi , Akira Asai , Takeshi Takagi , Tohru Saitoh , Yo Ichikawa , Yoshihiro Hara , Koichiro Yuki , Katsuya Nozawa , Koji Katayama , Yoshihiko Kanzawa
发明人： Teruhito Ohnishi , Akira Asai , Takeshi Takagi , Tohru Saitoh , Yo Ichikawa , Yoshihiro Hara , Koichiro Yuki , Katsuya Nozawa , Koji Katayama , Yoshihiko Kanzawa
IPC分类号： H01L2972
CPC分类号： H01L21/76237 , H01L21/8249
摘要： In a bipolar transistor block, a base layer (20a) of SiGe single crystals and an emitter layer (26) of almost 100% of Si single crystals are stacked in this order over a collector diffused layer (9). Over both edges of the base layer (20a), a base undercoat insulating film (5a) and base extended electrodes (22) made of polysilicon are provided. The base layer (20a) has a peripheral portion with a thickness equal to that of the base undercoat insulating film (5a) and a center portion thicker than the peripheral portion. The base undercoat insulating film (5a) and gate insulating films (5b and 5c) for a CMOS block are made of the same oxide film. A stress resulting from a difference in thermal expansion coefficient between the SiGe layer as the base layer and the base undercoat insulating film 5a can be reduced, and a highly reliable BiCMOS device is realized.
摘要翻译：在双极晶体管块中，SiGe单晶的基极层（20a）和几乎100％的Si单晶的发射极层（26）依次层叠在集电极扩散层（9）上。在基底层（20a）的两个边缘上设置有由多晶硅制成的基底底涂层绝缘膜（5a）和基底延伸电极（22）。基底层（20a）具有与基底底涂层绝缘膜（5a）的厚度相等的周边部分和比周边部分厚的中心部分。用于CMOS块的基底涂层绝缘膜（5a）和栅极绝缘膜（5b和5c）由相同的氧化物膜制成。由于作为基底层的SiGe层与基底底涂层绝缘膜5a之间的热膨胀系数的差异导致的应力可以降低，并且实现了高可靠性的BiCMOS器件。

4. 发明授权

US06852602B2 Semiconductor crystal film and method for preparation thereof 失效
标题翻译：半导体晶体膜及其制备方法
公开(公告)号：US06852602B2
公开(公告)日：2005-02-08
申请号：US10298000
申请日：2002-01-30
申请人： Yoshihiko Kanzawa , Tohru Saitoh , Katsuya Nozawa , Minoru Kubo , Yoshihiro Hara , Takeshi Takagi , Takahiro Kawashima
发明人： Yoshihiko Kanzawa , Tohru Saitoh , Katsuya Nozawa , Minoru Kubo , Yoshihiro Hara , Takeshi Takagi , Takahiro Kawashima
IPC分类号： H01L21/205 , H01L29/15 , H01L29/24 , H01L29/737 , H01L29/80 , H01L21/331
CPC分类号： H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02505 , H01L21/02507 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02661 , H01L29/155 , H01L29/1608 , H01L29/7378 , H01L29/802
摘要： A multi-layer film 10 is formed by stacking a Si1-x1-y1Gex1Cy1 layer (0≦x1 y2) having a high Ge mole fraction, e.g., a Si0.2Ge0.8 layer 12. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.
摘要翻译：通过层叠具有小Ge摩尔分数的Si1-x1-y1Gex1Cy1层（0 <= x1 <1和0 y2），例如Si0.2Ge0.8层以这种方式，多层膜用作结合到晶格点中的C原子的SiGeC层的范围延伸到Ge摩尔分数高的高度。

5. 发明授权

US06917075B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06917075B2
公开(公告)日：2005-07-12
申请号：US10752409
申请日：2004-01-07
申请人： Akira Inoue , Akira Asai , Teruhito Ohnishi , Haruyuki Sorada , Yoshihiro Hara , Takeshi Takagi
发明人： Akira Inoue , Akira Asai , Teruhito Ohnishi , Haruyuki Sorada , Yoshihiro Hara , Takeshi Takagi
IPC分类号： H01L21/336 , H01L21/768 , H01L29/78 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66772 , H01L21/76895 , H01L29/783 , H01L29/78615 , H01L29/78621
摘要： A semiconductor device and a method of fabricating the same according to this invention are such that: a gate insulator is formed over a predetermined region of a semiconductor substrate; a gate electrode is formed on the gate insulator; source and drain regions respectively formed in portions of the predetermined region that are situated on both sides of the gate electrode in plan view; a body region formed by a region of the predetermined region exclusive of the source and drain regions; and a contact electrically interconnecting the gate electrode and the body region, wherein a portion of the contact which is connected to the gate electrode is formed to intersect the gate electrode in plan view.
摘要翻译：根据本发明的半导体器件及其制造方法是：在半导体衬底的预定区域上形成栅极绝缘体; 栅电极形成在栅极绝缘体上; 源极和漏极区域分别形成在预定区域的位于栅极电极的两侧的部分中; 由不同于所述源极和漏极区域的所述预定区域的区域形成的体区; 以及使所述栅电极和所述体区域电连接的触点，其中，与所述栅电极连接的所述触点的一部分在平面图中形成为与所述栅电极相交。

6. 发明申请

US20050087803A1 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050087803A1
公开(公告)日：2005-04-28
申请号：US10997127
申请日：2004-11-24
申请人： Yoshihiro Hara , Akira Asai , Gaku Sugahara , Haruyuki Sorada , Teruhito Ohnishi
发明人： Yoshihiro Hara , Akira Asai , Gaku Sugahara , Haruyuki Sorada , Teruhito Ohnishi
IPC分类号： H01L21/762 , H01L21/8234 , H01L29/10 , H01L27/01 , H01L27/12 , H01L29/06 , H01L29/76 , H01L31/062
CPC分类号： H01L29/1054 , H01L21/76224 , H01L21/823481 , Y10S438/933
摘要： On an Si substrate 1, a buffer layer 2, a SiGe layer 3, and an Si cap layer 4 are formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trench 7a is formed so as to reach the Si substrate 1 and have the side faces of the SiGe layer 3 exposed. Then, the surface of the trench 7a is subjected to heat treatment for one hour at 750° C. so that Ge contained in a surface portion of the SiGe layer 3 is evaporated. Thus, a Ge evaporated portion 8 having a lower Ge content than that of other part of the SiGe layer 3 is formed in part of the SiGe layer 3 exposed at part of the trench 7a. Thereafter, the walls of the trench 7a are oxidized.
摘要翻译：在Si衬底1上形成缓冲层2，SiGe层3和Si覆盖层4。在基板上形成掩模，然后对基板进行图案化。以这种方式，形成沟槽7a以到达Si衬底1并且暴露SiGe层3的侧面。然后，将沟槽7a的表面在750℃下进行1小时的热处理，使得包含在SiGe层3的表面部分中的Ge蒸发。因此，在沟槽7a的一部分暴露的SiGe层3的一部分，形成Ge含量低于SiGe层3的Ge含量低的Ge蒸发部分8。此后，沟槽7a的壁被氧化。

7. 发明授权

US06861316B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06861316B2
公开(公告)日：2005-03-01
申请号：US10637212
申请日：2003-08-08
申请人： Yoshihiro Hara , Akira Asai , Gaku Sugahara , Haruyuki Sorada , Teruhito Ohnishi
发明人： Yoshihiro Hara , Akira Asai , Gaku Sugahara , Haruyuki Sorada , Teruhito Ohnishi
IPC分类号： H01L21/762 , H01L21/8234 , H01L29/10 , H01L21/336
CPC分类号： H01L29/1054 , H01L21/76224 , H01L21/823481 , Y10S438/933
摘要： On an Si substrate 1, a buffer layer 2, a SiGe layer 3, and an Si cap layer 4 are formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trench 7a is formed so as to reach the Si substrate 1 and have the side faces of the SiGe layer 3 exposed. Then, the surface of the trench 7a is subjected to heat treatment for one hour at 750° C. so that Ge contained in a surface portion of the SiGe layer 3 is evaporated. Thus, a Ge evaporated portion 8 having a lower Ge content than that of other part of the SiGe layer 3 is formed in part of the SiGe layer 3 exposed at part of the trench 7a. Thereafter, the walls of the trench 7a are oxidized.
摘要翻译：在Si衬底1上形成缓冲层2，SiGe层3和Si覆盖层4。在基板上形成掩模，然后对基板进行图案化。以这种方式，形成沟槽7a以到达Si衬底1并且暴露SiGe层3的侧面。然后，将沟槽7a的表面在750℃下进行1小时的热处理，使得包含在SiGe层3的表面部分中的Ge蒸发。因此，在沟槽7a的一部分暴露的SiGe层3的一部分，形成Ge含量低于SiGe层3的Ge含量低的Ge蒸镀部8。此后，沟槽7a的壁被氧化。

8. 发明授权

US07145168B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07145168B2
公开(公告)日：2006-12-05
申请号：US10997127
申请日：2004-11-24
申请人： Yoshihiro Hara , Akira Asai , Gaku Sugahara , Haruyuki Sorada , Teruhito Ohnishi
发明人： Yoshihiro Hara , Akira Asai , Gaku Sugahara , Haruyuki Sorada , Teruhito Ohnishi
IPC分类号： H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/1054 , H01L21/76224 , H01L21/823481 , Y10S438/933
摘要： On an Si substrate 1, a buffer layer 2, a SiGe layer 3, and an Si cap layer 4 are formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trench 7a is formed so as to reach the Si substrate 1 and have the side faces of the SiGe layer 3 exposed. Then, the surface of the trench 7a is subjected to heat treatment for one hour at 750° C. so that Ge contained in a surface portion of the SiGe layer 3 is evaporated. Thus, a Ge evaporated portion 8 having a lower Ge content than that of other part of the SiGe layer 3 is formed in part of the SiGe layer 3 exposed at part of the trench 7a. Thereafter, the walls of the trench 7a are oxidized.
摘要翻译：在Si衬底1上形成缓冲层2，SiGe层3和Si覆盖层4。在基板上形成掩模，然后对基板进行图案化。以这种方式，形成沟槽7a以到达Si衬底1并且暴露SiGe层3的侧面。然后，将沟槽7a的表面在750℃下进行1小时的热处理，使得包含在SiGe层3的表面部分中的Ge蒸发。因此，在沟槽7a的一部分暴露的SiGe层3的一部分，形成Ge含量低于SiGe层3的Ge含量低的Ge蒸发部分8。此后，沟槽7a的壁被氧化。

9. 发明授权

US07170110B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07170110B2
公开(公告)日：2007-01-30
申请号：US10983610
申请日：2004-11-09
申请人： Akira Inoue , Takeshi Takagi , Yoshihiro Hara , Minoru Kubo
发明人： Akira Inoue , Takeshi Takagi , Yoshihiro Hara , Minoru Kubo
IPC分类号： H01L29/161 , H01L29/772
CPC分类号： H01L29/802 , H01L21/823807 , H01L21/84 , H01L27/092 , H01L27/10873 , H01L27/11502 , H01L27/11507 , H01L27/1203 , H01L27/1214 , H01L27/1222 , H01L28/55 , H01L29/1054 , H01L29/783 , H01L29/78687
摘要： A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.
摘要翻译：依次沉积硅衬底101上的氧化硅膜102，Pt膜103x，Ti膜104x和PZT膜105x。将Si衬底101放置在室106中，使得PZT膜105x被EHF波108照射。用EHF波照射局部加热电介质膜，例如PZT膜。结果，可以改善例如电介质膜的泄漏特性，而不会对形成在Si衬底101上的器件产生不利影响。

10. 发明申请

US20060145245A1 Field-effect transistor, its manufacturing method, and complementary field-effect transistor 审中-公开
标题翻译：场效应晶体管，其制造方法和互补场效应晶体管
公开(公告)号：US20060145245A1
公开(公告)日：2006-07-06
申请号：US10544486
申请日：2004-02-09
申请人： Yoshihiro Hara , Takeshi Takagi
发明人： Yoshihiro Hara , Takeshi Takagi
IPC分类号： H01L29/76
CPC分类号： H01L29/783 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L27/092
摘要： A field effect transistor comprises: a semiconductor substrate; a semiconductor layer provided on the semiconductor substrate, the semiconductor layer including a body region which contains an impurity of a first conductivity type; a gate dielectric film provided on the semiconductor layer; a gate electrode provided on the gate dielectric film; and a source region and a drain region provided in the semiconductor layer at positions below the sides of the gate electrode, the source region and the drain region containing an impurity of a second conductivity type. The gate electrode and the body region are electrically short-circuited. In the semiconductor layer except for the source region and the drain region, at least part of a junction portion bordering on the source region or the drain region contains the impurity of the first conductivity type with a higher concentration than in the body region except for junction portions bordering on the source region and the drain region.
摘要翻译：场效应晶体管包括：半导体衬底; 设置在所述半导体衬底上的半导体层，所述半导体层包括含有第一导电类型杂质的体区; 设置在半导体层上的栅介质膜; 设置在栅极电介质膜上的栅电极; 以及源极区域和漏极区域，设置在半导体层中位于栅电极的侧面下方的位置处，源极区域和漏极区域包含第二导电类型的杂质。栅电极和体区电气短路。在除了源极区域和漏极区域之外的半导体层中，与源极区域或漏极区域接合的至少一部分接合部分含有比除了接合部分以外的体区域中的浓度高的第一导电型杂质在源极区域和漏极区域上接合的部分。

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