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1. 发明授权

US06645866B2 Method of fabricating a semiconductor device using trench isolation method including hydrogen annealing step 失效
标题翻译：使用包括氢退火步骤的沟槽隔离方法制造半导体器件的方法
公开(公告)号：US06645866B2
公开(公告)日：2003-11-11
申请号：US10319534
申请日：2002-12-16
申请人： Tai-su Park , Kyung-won Park , Jung-woo Park , Won-sang Song
发明人： Tai-su Park , Kyung-won Park , Jung-woo Park , Won-sang Song
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , Y10S438/958
摘要： A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.
摘要翻译：使用包括氢退火步骤的沟槽隔离方法制造半导体器件的方法，其中在半导体衬底上形成光致抗蚀剂图案，可以在形成光致抗蚀剂图案之前形成衬垫绝缘层，使用光致抗蚀剂蚀刻半导体衬底图案作为蚀刻掩模以形成沟槽，并且在沟槽中形成隔离层。为了消除在由隔离层限定的有源区域中产生的损伤，具有隔离层的半导体衬底在氢气氛中退火。

2. 发明授权

US06511888B1 Method of fabricating a semiconductor device using trench isolation method including hydrogen annealing step 失效
公开(公告)号：US06511888B1
公开(公告)日：2003-01-28
申请号：US09697302
申请日：2000-10-27
申请人： Tai-su Park , Kyung-won Park , Jung-woo Park , Won-sang Song
发明人： Tai-su Park , Kyung-won Park , Jung-woo Park , Won-sang Song
IPC分类号： H01L21336
CPC分类号： H01L21/76224 , Y10S438/958
摘要： A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.

3. 发明授权

US06627514B1 Semiconductor device having a Y-shaped isolation layer and simplified method for manufacturing the Y-shaped isolation layer to prevent divot formation 失效
标题翻译：具有Y形隔离层的半导体器件和用于制造Y形隔离层的简化方法以防止形成树脂
公开(公告)号：US06627514B1
公开(公告)日：2003-09-30
申请号：US09710225
申请日：2000-11-10
申请人： Tai-su Park , Kyung-won Park , Sung-jin Kim
发明人： Tai-su Park , Kyung-won Park , Sung-jin Kim
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A semiconductor device having a Y-shaped isolation layer and a method for manufacturing the same are provided. The semiconductor device includes a Y-shaped isolation layer, which comprises side walls characterized by first and second slopes on the sides of the isolation layer. The method for manufacturing the isolation layer includes the step of forming a trench in a semiconductor substrate using a photoresist pattern as an etching mask. Next, a thermal oxide film is formed on the surface of the semiconductor substrate, and then a thin nitride liner is formed on the thermal oxide film. The nitride liner prevents oxidation of the side wall of the trench and also acts as a planarization stop layer. Thereafter, a gap-filling isolation layer is formed to fill the trench such that the nitride liner is separated or thinner at the upper corners of the trench. Next, the gap-filling isolation layer is planarized using the nitride liner as a planarization stop layer. The nitride liner used as the planarization stop layer is removed. According to the present invention, formation of a divot at the boundary between an isolation region and an active region can be prevented.
摘要翻译：提供了具有Y形隔离层的半导体器件及其制造方法。该半导体器件包括Y形隔离层，其包括以隔离层侧面上的第一和第二斜面为特征的侧壁。用于制造隔离层的方法包括使用光致抗蚀剂图案作为蚀刻掩模在半导体衬底中形成沟槽的步骤。接下来，在半导体衬底的表面上形成热氧化膜，然后在热氧化膜上形成薄氮化物衬垫。氮化物衬垫防止沟槽的侧壁的氧化并且还用作平坦化停止层。此后，形成间隙填充隔离层以填充沟槽，使得氮化物衬垫在沟槽的上角分离或更薄。接下来，使用氮化物衬垫作为平坦化停止层来平坦化间隙填充隔离层。用作平坦化停止层的氮化物衬垫被去除。根据本发明，可以防止在隔离区域和有源区域之间的边界处形成边界。

4. 发明授权

US06465866B2 Trench isolation regions having trench liners with recessed ends 有权
标题翻译：具有凹槽端的沟槽衬套的沟槽隔离区
公开(公告)号：US06465866B2
公开(公告)日：2002-10-15
申请号：US09911096
申请日：2001-07-23
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.
摘要翻译：一种沟槽隔离结构，其通过对沟槽的顶部边缘进行舍入并增加在沟槽的顶部边缘处的氧化量，具有沟槽隔离结构的半导体器件和防止沟槽隔离结构的半导体器件，从而防止晶体管的隆起现象和反向窄宽度效应提供沟槽隔离方法。在这种沟槽隔离方法中，在半导体衬底的非有源区中形成沟槽。在沟槽的内壁上形成厚度为10至150埃的内壁氧化膜。在内壁氧化膜的表面上形成衬垫。沟槽填充有电介质膜。蚀刻衬垫的一部分，使得氮化硅衬垫的顶端从半导体衬底的表面凹陷。

5. 发明授权

US06258726B1 Method of forming isolation film for semiconductor devices 失效
标题翻译：形成半导体器件隔离膜的方法
公开(公告)号：US06258726B1
公开(公告)日：2001-07-10
申请号：US09412888
申请日：1999-10-05
申请人： Tai-Su Park , Yu-gyun Shin , Han-sin Lee , Kyung-won Park
发明人： Tai-Su Park , Yu-gyun Shin , Han-sin Lee , Kyung-won Park
IPC分类号： H01L21302
CPC分类号： H01L21/76224
摘要： A method of forming an isolation film forms a spacer for connecting the edge of an active region to the isolation film. The spacer is on the upper sidewall of a trench and smoothes the transition or step between the level of the isolation film and the level of the active region. Accordingly, a gate oxide film of a uniform thickness can be formed on the entire active region in a subsequent process, thus preventing degradation of the characteristics of the gate oxide film. The spacer can be formed using a sidewall spacer on the hard mask used for forming the trench. The sidewall spacer protects part of the isolation formed in the trench, and etching after removal of the sidewall spacer can round the protected portion to create the spacer. Furthermore, to dispel stresses and defects in the isolation film, annealing for densification of the isolation film can be performed at a high temperature such as about 1150° C. because the spacer mitigates the effects of shrinking or sagging of the isolation film.
摘要翻译：形成隔离膜的方法形成用于将有源区域的边缘连接到隔离膜的间隔物。间隔物位于沟槽的上侧壁上，并平滑了隔离膜的电平与有源区的电平之间的转变或台阶。因此，可以在随后的工艺中在整个有源区上形成均匀厚度的栅极氧化膜，从而防止栅极氧化膜的特性劣化。间隔物可以使用用于形成沟槽的硬掩模上的侧壁间隔物形成。侧壁间隔件保护形成在沟槽中的隔离部分，并且在去除侧壁间隔物之后的蚀刻可围绕被保护部分以形成隔离物。此外，为了消除隔离膜中的应力和缺陷，隔离膜的致密化退火可以在诸如约1150℃的高温下进行，因为间隔物减轻了隔离膜的收缩或下垂的影响。

6. 发明授权

US06537914B1 Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing 有权
标题翻译：集成电路器件隔离方法采用高选择性化学机械抛光
公开(公告)号：US06537914B1
公开(公告)日：2003-03-25
申请号：US09570225
申请日：2000-05-12
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee , Jung-yup Kim , Chang-ki Hong , Ho-kyu Kang
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee , Jung-yup Kim , Chang-ki Hong , Ho-kyu Kang
IPC分类号： H01L21302
CPC分类号： C09G1/02 , C09K3/1463 , H01L21/31053 , H01L21/76224
摘要： Trench isolation methods for integrated circuits may reduce irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. In particular, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO2 group abrasive to form an isolation layer in the trench. The CMP selectivity ratio of a slurry that includes a CeO2 group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.
摘要翻译：用于集成电路的沟槽隔离方法可以通过使用高选择性化学机械抛光（CMP）操作来减少形成隔离层的不规则性。特别地，蚀刻衬底表面以形成沟槽。然后在衬底表面和沟槽中形成绝缘层。绝缘层使用包含CeO 2基团研磨剂的浆料进行化学机械抛光，以在沟槽中形成隔离层。包括CeO 2基研磨剂的浆料的CMP选择比可能足以使基板表面用作CMP停止。结果，可以在衬底表面上保持更一致的抛光水平，这可能导致隔离层中更均匀的厚度。

7. 发明授权

US06331469B1 Trench isolation structure, semiconductor device having the same, and trench isolation method 有权
标题翻译：沟槽隔离结构，具有相同的半导体器件，以及沟槽隔离方法
公开(公告)号：US06331469B1
公开(公告)日：2001-12-18
申请号：US09684822
申请日：2000-10-10
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.
摘要翻译：一种沟槽隔离结构，其通过对沟槽的顶部边缘进行舍入并增加在沟槽的顶部边缘处的氧化量，具有沟槽隔离结构的半导体器件和防止沟槽隔离结构的半导体器件，从而防止晶体管的隆起现象和反向窄宽度效应提供沟槽隔离方法。在这种沟槽隔离方法中，在半导体衬底的非有源区中形成沟槽。在沟槽的内壁上形成厚度为10至150埃的内壁氧化膜。在内壁氧化膜的表面上形成衬垫。沟槽填充有电介质膜。蚀刻衬垫的一部分，使得氮化硅衬垫的顶端从半导体衬底的表面凹陷。

8. 发明授权

US06429107B2 Method for forming conductive contact of semiconductor device 有权
标题翻译：用于形成半导体器件的导电接触的方法
公开(公告)号：US06429107B2
公开(公告)日：2002-08-06
申请号：US09839855
申请日：2001-04-20
申请人： Hyoung-joon Kim , Byeong-yun Nam , Kyung-won Park
发明人： Hyoung-joon Kim , Byeong-yun Nam , Kyung-won Park
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/76801
摘要： A method for forming a conductive contact of a semiconductor device is provided. According to one aspect of the present invention, a dummy dielectric layer pattern having a dummy opening and an interdielectric layer pattern having a lower etch-rate than that of the dummy dielectric layer, for filling the dummy opening are formed on a semiconductor substrate. The dummy dielectric layer pattern using the interdielectric layer pattern as an etching mask is selectively removed, and a contact opening for exposing the semiconductor substrate of a portion in which the dummy dielectric layer pattern is located.
摘要翻译：提供一种用于形成半导体器件的导电接触的方法。根据本发明的一个方面，在半导体衬底上形成有用于填充虚拟开口的具有比虚拟电介质层低的蚀刻速率的虚拟开口和介电层图案的虚拟介电层图案。选择性地去除使用电介质层图案作为蚀刻掩模的虚拟介电层图案，以及用于使虚设电介质层图案所在的部分露出半导体基板的接触开口。

9. 发明授权

US06916764B2 Pt-Ru-M1-M2 quaternary metal catalyst based on Pt-Ru for direct methanol fuel cell 有权
标题翻译： Pt-Ru-M1-M2基于直接甲醇燃料电池的Pt-Ru的四元金属催化剂
公开(公告)号：US06916764B2
公开(公告)日：2005-07-12
申请号：US10242457
申请日：2002-09-13
申请人： Kyoung Hwan Choi , Seol-ah Lee , Yung-eun Sung , Kyung-won Park , Jong-ho Choi
发明人： Kyoung Hwan Choi , Seol-ah Lee , Yung-eun Sung , Kyung-won Park , Jong-ho Choi
IPC分类号： B01J23/46 , B01J23/40 , B01J23/89 , B01J37/03 , B01J37/16 , C22C5/04 , H01M4/86 , H01M4/90 , H01M4/92 , H01M8/10 , B01J23/56
CPC分类号： B01J23/40 , B01J23/892 , B01J37/03 , B01J37/16 , H01M4/8605 , H01M4/921 , H01M8/1009 , Y02E60/523
摘要： Provided is a Pt—Ru based quaternary metal anode catalyst for a direct methanol fuel cell (DMFC). The Pt—Ru based quaternary metal anode catalyst has high activity to methanol oxidation and strong resistance to catalyst poisoning due to carbon monoxide (CO), which is a byproduct of the methanol oxidation. Therefore, the Pt—Ru based quaternary metal anode catalyst can give high power density and can replace existing commercial catalysts.
摘要翻译：提供了一种用于直接甲醇燃料电池（DMFC）的Pt-Ru基季铵金属阳极催化剂。基于Pt-Ru的四元金属阳极催化剂对甲醇氧化具有高活性，并且由于甲醇氧化的副产物一氧化碳（CO）导致的催化剂中毒性强。因此，基于Pt-Ru的四元金属阳极催化剂可以提供高功率密度并且可以代替现有的商业催化剂。

10. 发明申请

US20060183296A1 Isolation method for semiconductor device 审中-公开
公开(公告)号：US20060183296A1
公开(公告)日：2006-08-17
申请号：US11398536
申请日：2006-04-06
申请人： Jae-yoon Yoo , Moon-han Park , Dong-ho Ahn , Sug-hun Hong , Kyung-won Park , Jeong-soo Lee
发明人： Jae-yoon Yoo , Moon-han Park , Dong-ho Ahn , Sug-hun Hong , Kyung-won Park , Jeong-soo Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： An isolation method for a semiconductor device where an insulating mask layer is formed on desired regions of a semiconductor substrate. A trench is formed to a desired depth in the semiconductor substrate using the insulating mask layer as a mask. An oxide layer is formed on the insulating mask layer and on the sidewall of the trench. A trench liner layer is formed on the oxide layer. An insulating filler layer is formed in the trench in the semiconductor substrate, on which the trench liner layer is formed, so as to fill the trench. The insulating mask layer is removed. According to the isolation method for a semiconductor device, it is possible to reduce dents from occurring along the edge of the trench, reduce a bird's beak type oxide layer from occurring at an interface between the insulating mask layers, decrease the leakage current, or improve the electrical characteristics, such as threshold voltage.

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