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1. 发明授权

US06258726B1 Method of forming isolation film for semiconductor devices 失效
标题翻译：形成半导体器件隔离膜的方法
公开(公告)号：US06258726B1
公开(公告)日：2001-07-10
申请号：US09412888
申请日：1999-10-05
申请人： Tai-Su Park , Yu-gyun Shin , Han-sin Lee , Kyung-won Park
发明人： Tai-Su Park , Yu-gyun Shin , Han-sin Lee , Kyung-won Park
IPC分类号： H01L21302
CPC分类号： H01L21/76224
摘要： A method of forming an isolation film forms a spacer for connecting the edge of an active region to the isolation film. The spacer is on the upper sidewall of a trench and smoothes the transition or step between the level of the isolation film and the level of the active region. Accordingly, a gate oxide film of a uniform thickness can be formed on the entire active region in a subsequent process, thus preventing degradation of the characteristics of the gate oxide film. The spacer can be formed using a sidewall spacer on the hard mask used for forming the trench. The sidewall spacer protects part of the isolation formed in the trench, and etching after removal of the sidewall spacer can round the protected portion to create the spacer. Furthermore, to dispel stresses and defects in the isolation film, annealing for densification of the isolation film can be performed at a high temperature such as about 1150° C. because the spacer mitigates the effects of shrinking or sagging of the isolation film.
摘要翻译：形成隔离膜的方法形成用于将有源区域的边缘连接到隔离膜的间隔物。间隔物位于沟槽的上侧壁上，并平滑了隔离膜的电平与有源区的电平之间的转变或台阶。因此，可以在随后的工艺中在整个有源区上形成均匀厚度的栅极氧化膜，从而防止栅极氧化膜的特性劣化。间隔物可以使用用于形成沟槽的硬掩模上的侧壁间隔物形成。侧壁间隔件保护形成在沟槽中的隔离部分，并且在去除侧壁间隔物之后的蚀刻可围绕被保护部分以形成隔离物。此外，为了消除隔离膜中的应力和缺陷，隔离膜的致密化退火可以在诸如约1150℃的高温下进行，因为间隔物减轻了隔离膜的收缩或下垂的影响。

2. 发明授权

US5858858A Annealing methods for forming isolation trenches 失效
标题翻译：用于形成隔离沟的退火方法
公开(公告)号：US5858858A
公开(公告)日：1999-01-12
申请号：US729453
申请日：1996-10-11
申请人： Tai-su Park , Moon-han Park , Yu-gyun Shin , Han-sin Lee
发明人： Tai-su Park , Moon-han Park , Yu-gyun Shin , Han-sin Lee
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： A method for forming a microelectronic structure includes the steps of forming a mask layer on a substrate, forming a trench in the exposed portion of the substrate, forming a layer of an insulating material which fills the trench and covers the mask layer, and annealing the insulating material at a temperature of at least about 1,150.degree. C. The annealing step can be performed for a period of time of about .5 hours to about 8 hours, and the annealing step can be performed in an inert atmosphere.
摘要翻译：一种形成微电子结构的方法包括以下步骤：在衬底上形成掩模层，在衬底的暴露部分形成沟槽，形成填充沟槽并覆盖掩模层的绝缘材料层，并退火绝缘材料在至少约1150℃的温度下进行。退火步骤可以进行约0.5小时至约8小时的时间，退火步骤可以在惰性气氛中进行。

3. 发明授权

US6121110A Trench isolation method for semiconductor device 失效
标题翻译：半导体器件的沟槽隔离方法
公开(公告)号：US6121110A
公开(公告)日：2000-09-19
申请号：US124093
申请日：1998-07-29
申请人： Soo-jin Hong , Yu-gyun Shin , Han-sin Lee , Hyun-cheol Choe
发明人： Soo-jin Hong , Yu-gyun Shin , Han-sin Lee , Hyun-cheol Choe
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： A trench isolation method is provided. In the trench isolation method, a pad oxide film, an oxidative film and an etching mask film are formed on a semiconductor substrate in sequence, and then a trench is formed in a field region of the semiconductor substrate. A oxide film is formed at the inner wall of the trench and the side walls of the oxidative film by oxidizing the semiconductor substrate. After filling the trench with a dielectric material, the pad oxide film, oxidative film and etching mask film formed in the active region are removed.
摘要翻译：提供沟槽隔离方法。在沟槽隔离方法中，顺序地在半导体衬底上形成衬垫氧化膜，氧化膜和蚀刻掩模膜，然后在半导体衬底的场区域中形成沟槽。通过氧化半导体衬底，在沟槽的内壁和氧化膜的侧壁上形成氧化膜。在用电介质材料填充沟槽之后，去除在活性区域中形成的衬垫氧化膜，氧化膜和蚀刻掩模膜。

4. 发明授权

US07968442B2 Fin field effect transistor and method of fabricating the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US07968442B2
公开(公告)日：2011-06-28
申请号：US12459660
申请日：2009-07-06
申请人： Jong-hoon Kang , Tai-su Park , Dong-chan Kim , Yu-gyun Shin , Jeong-do Ryu , Seong-hoon Jeong
发明人： Jong-hoon Kang , Tai-su Park , Dong-chan Kim , Yu-gyun Shin , Jeong-do Ryu , Seong-hoon Jeong
IPC分类号： H01L21/28
CPC分类号： H01L29/7854 , H01L29/66795
摘要： A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.
摘要翻译：翅片场效应晶体管包括从半导体衬底突出的鳍片，形成为覆盖鳍片的上表面和侧表面的栅极绝缘层，以及跨过鳍状物形成以覆盖栅极绝缘层的栅电极。鳍的上边缘是圆形的，使得通过栅电极集中地施加到鳍的上边缘的电场被分散。形成在鳍的上表面上的栅极绝缘层的一部分的厚度大于形成在鳍的侧表面上的栅极绝缘层的一部分的厚度，以便减少通过栅电极。

5. 发明申请

US20100109057A1 Fin field effect transistor and method of fabricating the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US20100109057A1
公开(公告)日：2010-05-06
申请号：US12459660
申请日：2009-07-06
申请人： Jong-hoon Kang , Tai-su Park , Dong-chan Kim , Yu-gyun Shin , Jeong-do Ryu , Seong-hoon Jeong
发明人： Jong-hoon Kang , Tai-su Park , Dong-chan Kim , Yu-gyun Shin , Jeong-do Ryu , Seong-hoon Jeong
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7854 , H01L29/66795
摘要： A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.
摘要翻译：翅片场效应晶体管包括从半导体衬底突出的鳍片，形成为覆盖鳍片的上表面和侧表面的栅极绝缘层，以及跨过鳍状物形成以覆盖栅极绝缘层的栅电极。鳍的上边缘是圆形的，使得通过栅电极集中地施加到鳍的上边缘的电场被分散。形成在鳍的上表面上的栅极绝缘层的一部分的厚度大于形成在鳍的侧表面上的栅极绝缘层的一部分的厚度，以便减少通过栅电极。

6. 发明申请

US20060205186A1 High dielectric film and related method of manufacture 有权
公开(公告)号：US20060205186A1
公开(公告)日：2006-09-14
申请号：US11359404
申请日：2006-02-23
申请人： Hong-bae Park , Yu-gyun Shin , Sang-bom Kang
发明人： Hong-bae Park , Yu-gyun Shin , Sang-bom Kang
IPC分类号： H01L21/20
CPC分类号： H01L21/0228 , C23C16/308 , C23C16/45531 , H01L21/02142 , H01L21/02194 , H01L21/02274 , H01L21/3141 , H01L21/3145 , H01L21/31645
摘要： A method of forming a high dielectric film for a semiconductor device comprises supplying a first source gas to a reaction chamber during a first time interval, supplying a first reactant gas to the reaction chamber during a second time interval after the first time interval, supplying a second source gas to the reaction chamber for a third time interval after the second time interval, supplying a second reactant gas to the reaction chamber for a fourth time interval after the third time interval, and supplying an additive gas including nitrogen to the reaction chamber during a fifth time interval.

7. 发明授权

US5641705A Device isolation method of semiconductor device 失效
标题翻译：半导体器件的器件隔离方法
公开(公告)号：US5641705A
公开(公告)日：1997-06-24
申请号：US470914
申请日：1995-06-06
申请人： Dong-ho Ahn , Seong-joon Ahn , Yu-gyun Shin , Yun-gi Kim
发明人： Dong-ho Ahn , Seong-joon Ahn , Yu-gyun Shin , Yun-gi Kim
IPC分类号： H01L21/316 , H01L21/32 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76205 , H01L21/32
摘要： In a device isolation method for a semiconductor device, after a pad oxide layer and a nitride layer are formed on a semiconductor substrate, the nitride layer located above the device isolation region is removed. An undercut is formed under the nitride by partially etching the pad oxide layer. After a first oxide layer is formed on the exposed substrate and a polysilicon spacer is formed on the sidewalls of the nitride layer, a void is formed in the oxide layer under the nitride layer which is formed on the active region by oxidizing the resultant structure in which the polysilicon spacer is formed at a temperature above 950.degree. C. Thus, good cell definition and stable device isolation can be realized, while solving the typical problem of conventional LOCOS methods by forming the void intentionally in the pad oxide layer thickened by bird's beak punch through.
摘要翻译：在半导体器件的器件隔离方法中，在衬底氧化物层和氮化物层形成在半导体衬底上之后，去除位于器件隔离区上方的氮化物层。通过部分蚀刻衬垫氧化物层，在氮化物之下形成底切。在暴露的基板上形成第一氧化物层并在氮化物层的侧壁上形成多晶硅间隔物之后，在形成于有源区上的氮化物层下面的氧化物层中形成空穴，其中多晶硅间隔物在高于950℃的温度下形成。因此，通过在通过鸟喙加厚的垫氧化物层中有意地形成空穴来解决常规LOCOS方法的典型问题，可以实现良好的电池定义和稳定的器件隔离穿透

8. 发明申请

US20100213541A1 SEMICONDUCTOR DEVICE HAVING RECESS CHANNEL STRUCTURE 审中-公开
标题翻译：具有输入通道结构的半导体器件
公开(公告)号：US20100213541A1
公开(公告)日：2010-08-26
申请号：US12699650
申请日：2010-02-03
申请人： In-sang Jeon , Si-hyung Lee , Jong-ryeol Yoo , Yu-gyun Shin , Suk-hun Choi
发明人： In-sang Jeon , Si-hyung Lee , Jong-ryeol Yoo , Yu-gyun Shin , Suk-hun Choi
IPC分类号： H01L29/78
CPC分类号： H01L29/4236 , H01L21/28088 , H01L21/28202 , H01L27/10876 , H01L27/11 , H01L27/11517 , H01L29/4966 , H01L29/518
摘要： An integrated circuit device includes a semiconductor substrate including an active region defined by an isolation region and having at least one trench therein, a gate insulating layer formed in the at least one trench, a gate electrode layer having a nano-crystalline structure disposed on the gate insulating layer and a word line on the gate electrode layer in the at least one trench. The device may further include a capping layer on the word line.
摘要翻译：一种集成电路器件包括：半导体衬底，包括由隔离区限定的有源区，其中至少有一个沟槽;在该至少一个沟槽中形成的栅极绝缘层，具有纳米晶体结构的栅电极层，栅极绝缘层和在至少一个沟槽中的栅极电极层上的字线。该装置还可以包括字线上的覆盖层。

9. 发明申请

US20100197092A1 Method of Manufacturing Semiconductor Device Having Stress Creating Layer 有权
标题翻译：制造具有应力创造层的半导体器件的方法
公开(公告)号：US20100197092A1
公开(公告)日：2010-08-05
申请号：US12693080
申请日：2010-01-25
申请人： Jin-bum Kim , Wook-je Kim , Yu-gyun Shin , Kwan-heum Lee , Sun-Ghil Lee
发明人： Jin-bum Kim , Wook-je Kim , Yu-gyun Shin , Kwan-heum Lee , Sun-Ghil Lee
IPC分类号： H01L21/8238 , H01L21/20
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： Provided is a simplified method of manufacturing a semiconductor device having a stress creating layer. A first conductive first impurity region is formed on a semiconductor substrate on both sides of a first gate of a first area of the semiconductor substrate, and a second conductive second impurity region is formed on the semiconductor substrate on both sides of a second gate of a second area. First and second spacers are formed on sidewalls of the first and second gates, respectively. First and second semiconductor layers are formed in portions of the semiconductor substrate so as to contact the first and second impurity regions, respectively. The second semiconductor layer is removed. First and second barrier layers are formed in the first and second contact holes of the insulation layer, respectively.
摘要翻译：提供了一种制造具有应力产生层的半导体器件的简化方法。在半导体衬底的第一区域的第一栅极的两侧上的半导体衬底上形成第一导电第一杂质区，并且在半导体衬底的第二栅极的两侧的半导体衬底上形成第二导电第二杂质区第二区。第一和第二间隔物分别形成在第一和第二栅极的侧壁上。第一半导体层和第二半导体层分别形成在半导体衬底的部分中，以分别接触第一和第二杂质区。去除第二半导体层。第一和第二阻挡层分别形成在绝缘层的第一和第二接触孔中。

10. 发明授权

US07521331B2 High dielectric film and related method of manufacture 有权
标题翻译：高介电膜及相关制造方法
公开(公告)号：US07521331B2
公开(公告)日：2009-04-21
申请号：US11359404
申请日：2006-02-23
申请人： Hong-bae Park , Yu-gyun Shin , Sang-bom Kang
发明人： Hong-bae Park , Yu-gyun Shin , Sang-bom Kang
IPC分类号： H01L21/76
CPC分类号： H01L21/0228 , C23C16/308 , C23C16/45531 , H01L21/02142 , H01L21/02194 , H01L21/02274 , H01L21/3141 , H01L21/3145 , H01L21/31645
摘要： A method of forming a high dielectric film for a semiconductor device comprises supplying a first source gas to a reaction chamber during a first time interval, supplying a first reactant gas to the reaction chamber during a second time interval after the first time interval, supplying a second source gas to the reaction chamber for a third time interval after the second time interval, supplying a second reactant gas to the reaction chamber for a fourth time interval after the third time interval, and supplying an additive gas including nitrogen to the reaction chamber during a fifth time interval.
摘要翻译：形成用于半导体器件的高电介质膜的方法包括：在第一时间间隔内将第一源气体供应到反应室，在第一时间间隔之后的第二时间间隔期间将第一反应气体供应到反应室，在所述第二时间间隔之后的第三时间间隔内将第二源气体供应到所述反应室，在所述第三时间间隔之后，将第二反应气体供应到所述反应室中第四时间间隔，并且在所述第三时间间隔内向所述反应室供应包含氮气的添加剂气体第五个时间间隔。

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