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1. 发明授权

US08691649B2 Methods of forming recessed channel array transistors and methods of manufacturing semiconductor devices 有权
标题翻译：形成凹槽阵列晶体管的方法和制造半导体器件的方法
公开(公告)号：US08691649B2
公开(公告)日：2014-04-08
申请号：US13151494
申请日：2011-06-02
申请人： Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L21/28211 , H01L21/823412 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/11 , H01L29/4236 , H01L29/51 , H01L29/66621 , H01L29/7851
摘要： In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.
摘要翻译：在制造凹陷通道阵列晶体管的方法中，可以在衬底的有源区中形成凹部。可以在衬底上进行等离子体氧化处理，以在凹槽的内表面和衬底的上表面上形成预备栅氧化层。可以在预选择栅极氧化物层的表面吸收水分以形成栅极氧化物层。可以在栅极氧化物层上形成栅电极以填充凹部。源极/漏极区域可以形成在栅电极的两侧的衬底的上表面中。因此，氧化物层可以具有均匀的厚度分布和致密结构。

2. 发明授权

US07807543B2 Methods of manufacturing trench isolation structures using selective plasma ion immersion implantation and deposition (PIIID) 有权
标题翻译：使用选择性等离子体离子浸入和沉积（PIIID）制造沟槽隔离结构的方法
公开(公告)号：US07807543B2
公开(公告)日：2010-10-05
申请号：US12134760
申请日：2008-06-06
申请人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
发明人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823456 , H01L27/0921 , H01L27/105
摘要： A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.
摘要翻译：通过在衬底中形成沟槽并且在衬底中的沟槽的子集上选择性地执行等离子体离子注入植入和沉积（PIIID）来制造半导体器件。 PIIID可以仅在衬底中的至少一个沟槽的表面的一部分上进行。半导体器件可以包括其中具有第一，第二和第三沟槽的半导体衬底以及不对第一沟槽进行线条化的氧化物衬层，其不线性化第二沟槽并且部分地对第三沟槽进行排列。

3. 发明申请

US20090325356A1 METHODS OF FORMING A LOW TEMPERATURE DEPOSITION LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：形成低温沉积层的方法和使用其制造半导体器件的方法
公开(公告)号：US20090325356A1
公开(公告)日：2009-12-31
申请号：US12432500
申请日：2009-04-29
申请人： Dong-Woon SHIN , Si-Young Choi , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Dong-Woon SHIN , Si-Young Choi , Tai-Su Park , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L21/336 , H01L21/31 , H01L21/426
CPC分类号： H01L21/02274 , H01L21/0217 , H01L21/02211 , H01L21/2236 , H01L21/2652 , H01L21/26546 , H01L21/2658 , H01L21/3185 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/6659
摘要： Provided are methods of forming a low temperature deposition layer and methods of manufacturing a semiconductor device using the same. The method of manufacturing a semiconductor device comprises forming a mask layer exposing a gate pattern on a substrate on which the gate pattern is formed, forming a sacrifice layer on the mask layer and on a substrate not covered by the mask layer using a plasma ion immersion implantation and deposition (PIIID), and doping a substrate adjacent to both sidewalls of the gate pattern with an impurity.
摘要翻译：提供形成低温沉积层的方法和使用其制造半导体器件的方法。制造半导体器件的方法包括：在掩模层上形成掩模层，在其上形成栅极图案的衬底上露出栅极图案，在掩模层上形成牺牲层，并在未被掩模层覆盖的衬底上使用等离子体离子浸没注入和沉积（PIIID），并且用杂质掺杂与栅极图案的两个侧壁相邻的衬底。

4. 发明授权

US07459359B2 Methods of fabricating vertical channel field effect transistors having insulating layers thereon 有权
标题翻译：制造其上具有绝缘层的垂直沟道场效应晶体管的方法
公开(公告)号：US07459359B2
公开(公告)日：2008-12-02
申请号：US11556804
申请日：2006-11-06
申请人： Tai-Su Park , Eui-Joon Yoon , U-In Chung , Si-Young Choi , Jong-Ho Lee
发明人： Tai-Su Park , Eui-Joon Yoon , U-In Chung , Si-Young Choi , Jong-Ho Lee
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The method may also include forming a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, forming a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and forming a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction.
摘要翻译：形成场效应晶体管的方法包括形成从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，并且形成在垂直沟道的侧壁上朝向衬底延伸的绝缘层，超出源/漏区结。该方法还可以包括在侧壁上形成远离衬底延伸到绝缘层的氮化物层，形成在侧壁上延伸的第二绝缘层，所述第二绝缘层通过氮化物层从沟道分离，并形成栅电极在侧壁上朝向衬底延伸超过源/漏区结。

5. 发明申请

US20080176387A1 PLASMA DOPING METHODS USING MULTIPLE SOURCE GASES 审中-公开
标题翻译：使用多种源气体的等离子体掺杂方法
公开(公告)号：US20080176387A1
公开(公告)日：2008-07-24
申请号：US11753791
申请日：2007-05-25
申请人： Jong-hoon Kang , Tai-su Park , Si-young Choi , Min-jin Kim
发明人： Jong-hoon Kang , Tai-su Park , Si-young Choi , Min-jin Kim
IPC分类号： H01L21/265
CPC分类号： H01L21/2236 , H01L21/28035 , H01L21/3215 , H01L21/32155 , H01L29/4916
摘要： A plasma doping method includes providing a substrate including a layer to be doped inside a chamber, and supplying first and second source gases to the layer to achieve a desired doping concentration. The first source gas includes a component configured to increase a thickness of the layer, and the second gas includes a component configured to reduce a thickness of the layer.
摘要翻译：等离子体掺杂方法包括提供包括在室内掺杂的层的衬底，以及将第一和第二源气体供应到层以实现期望的掺杂浓度。第一源气体包括构造成增加层的厚度的部件，并且第二气体包括构造成减小层的厚度的部件。

6. 发明申请

US20070054453A1 Methods of forming integrated circuit memory devices having a charge storing layer formed by plasma doping 审中-公开
标题翻译：形成具有通过等离子体掺杂形成的电荷存储层的集成电路存储器件的方法
公开(公告)号：US20070054453A1
公开(公告)日：2007-03-08
申请号：US11504023
申请日：2006-08-14
申请人： Gyoung-Ho Buh , Tai-Su Park , Chang-Woo Ryoo , Jong-Ryeol Yoo , Young-Chang Song
发明人： Gyoung-Ho Buh , Tai-Su Park , Chang-Woo Ryoo , Jong-Ryeol Yoo , Young-Chang Song
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L29/42344 , H01L29/66833
摘要： Methods of forming an integrated circuit memory device include forming a dielectric layer on a substrate and forming a charge storing layer on an upper surface of the dielectric layer using a plasma doping process with a remaining portion of the dielectric layer under the charge storing layer defining a tunnel dielectric layer. A blocking dielectric layer is formed on the charge storing layer and a gate electrode layer is formed on the blocking dielectric layer.
摘要翻译：形成集成电路存储器件的方法包括在衬底上形成电介质层，并使用等离子体掺杂工艺在电介质层的上表面上形成电荷存储层，其中电荷存储层下面的介电层的剩余部分限定了隧道介电层。在电荷存储层上形成阻挡电介质层，在阻挡电介质层上形成栅电极层。

7. 发明申请

US20070020827A1 Methods of forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US20070020827A1
公开(公告)日：2007-01-25
申请号：US11490613
申请日：2006-07-21
申请人： Gyoung-Ho Buh , Chang-Woo Ryoo , Yu-Gyun Shin , Tai-Su Park , Jin-Wook Lee
发明人： Gyoung-Ho Buh , Chang-Woo Ryoo , Yu-Gyun Shin , Tai-Su Park , Jin-Wook Lee
IPC分类号： H01L21/84 , H01L21/8234 , H01L21/336 , H01L21/00
CPC分类号： H01L29/7851 , H01L29/42392 , H01L29/66795 , H01L29/66803
摘要： A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type impurity elements, and the second source gas includes a dilution element regardless of the electrical characteristic of a doped region.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成由半导体形成的三维结构，并且通过使用第一源气体和第二源气体进行等离子体掺杂工艺，对三维结构进行各向同性地掺杂。第一源气体包括n型或p型杂质元素，第二源气体包括稀释元件，而与掺杂区域的电特性无关。

8. 发明授权

US06511888B1 Method of fabricating a semiconductor device using trench isolation method including hydrogen annealing step 失效
公开(公告)号：US06511888B1
公开(公告)日：2003-01-28
申请号：US09697302
申请日：2000-10-27
申请人： Tai-su Park , Kyung-won Park , Jung-woo Park , Won-sang Song
发明人： Tai-su Park , Kyung-won Park , Jung-woo Park , Won-sang Song
IPC分类号： H01L21336
CPC分类号： H01L21/76224 , Y10S438/958
摘要： A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.

9. 发明授权

US06258726B1 Method of forming isolation film for semiconductor devices 失效
标题翻译：形成半导体器件隔离膜的方法
公开(公告)号：US06258726B1
公开(公告)日：2001-07-10
申请号：US09412888
申请日：1999-10-05
申请人： Tai-Su Park , Yu-gyun Shin , Han-sin Lee , Kyung-won Park
发明人： Tai-Su Park , Yu-gyun Shin , Han-sin Lee , Kyung-won Park
IPC分类号： H01L21302
CPC分类号： H01L21/76224
摘要： A method of forming an isolation film forms a spacer for connecting the edge of an active region to the isolation film. The spacer is on the upper sidewall of a trench and smoothes the transition or step between the level of the isolation film and the level of the active region. Accordingly, a gate oxide film of a uniform thickness can be formed on the entire active region in a subsequent process, thus preventing degradation of the characteristics of the gate oxide film. The spacer can be formed using a sidewall spacer on the hard mask used for forming the trench. The sidewall spacer protects part of the isolation formed in the trench, and etching after removal of the sidewall spacer can round the protected portion to create the spacer. Furthermore, to dispel stresses and defects in the isolation film, annealing for densification of the isolation film can be performed at a high temperature such as about 1150° C. because the spacer mitigates the effects of shrinking or sagging of the isolation film.
摘要翻译：形成隔离膜的方法形成用于将有源区域的边缘连接到隔离膜的间隔物。间隔物位于沟槽的上侧壁上，并平滑了隔离膜的电平与有源区的电平之间的转变或台阶。因此，可以在随后的工艺中在整个有源区上形成均匀厚度的栅极氧化膜，从而防止栅极氧化膜的特性劣化。间隔物可以使用用于形成沟槽的硬掩模上的侧壁间隔物形成。侧壁间隔件保护形成在沟槽中的隔离部分，并且在去除侧壁间隔物之后的蚀刻可围绕被保护部分以形成隔离物。此外，为了消除隔离膜中的应力和缺陷，隔离膜的致密化退火可以在诸如约1150℃的高温下进行，因为间隔物减轻了隔离膜的收缩或下垂的影响。

10. 发明授权

US08835275B2 Semiconductor devices having nitrided gate insulating layer and methods of fabricating the same 有权
标题翻译：具有氮化栅极绝缘层的半导体器件及其制造方法
公开(公告)号：US08835275B2
公开(公告)日：2014-09-16
申请号：US13604352
申请日：2012-09-05
申请人： Tai-Su Park , Jin-Hyuk Choi , Sang-Chul Han , Jung-Sup Oh , Young-Dong Lee
发明人： Tai-Su Park , Jin-Hyuk Choi , Sang-Chul Han , Jung-Sup Oh , Young-Dong Lee
IPC分类号： H01L21/28
CPC分类号： C23C16/34 , C23C28/04 , H01L21/0214 , H01L21/02332 , H01L21/0234 , H01L21/28202 , H01L29/0657 , H01L29/42356 , H01L29/518 , H01L29/66621
摘要： Semiconductor devices, and methods of fabricating the same, include forming device isolation regions in a substrate to define active regions, forming gate trenches in the substrate to expose the active regions and device isolation regions, conformally forming a preliminary gate insulating layer including silicon oxide on the active regions exposed in the grate trenches, nitriding the preliminary gate insulating layer using a radio-frequency bias having a frequency of about 13.56 MHz and power between about 100 W and about 300 W to form a nitrided preliminary gate insulating layer including silicon oxynitride, forming a gate electrode material layer on the nitride preliminary gate insulating layer, partially removing the nitrided preliminary gate insulating layer and the gate electrode material layer to respectively form a gate insulating layer and a gate electrode layer, and forming a gate capping layer on the gate electrode layer to fill the gate trenches.
摘要翻译：半导体器件及其制造方法包括在衬底中形成器件隔离区域以限定有源区域，在衬底中形成栅极沟槽以暴露有源区域和器件隔离区域，以共形形成包括氧化硅在内的初步栅极绝缘层在栅极沟槽中暴露的有源区域，使用频率约13.56MHz，功率在约100W至约300W之间的射频偏压来对初级栅极绝缘层进行氮化，以形成氮化预备栅极绝缘层，其包括氮氧化硅，在氮化物预选绝缘层上形成栅电极材料层，部分去除氮化预栅极绝缘层和栅电极材料层，分别形成栅极绝缘层和栅极电极层，并在栅极上形成栅极覆盖层电极层填充栅极沟槽。

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