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1. 发明授权

US06465866B2 Trench isolation regions having trench liners with recessed ends 有权
标题翻译：具有凹槽端的沟槽衬套的沟槽隔离区
公开(公告)号：US06465866B2
公开(公告)日：2002-10-15
申请号：US09911096
申请日：2001-07-23
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.
摘要翻译：一种沟槽隔离结构，其通过对沟槽的顶部边缘进行舍入并增加在沟槽的顶部边缘处的氧化量，具有沟槽隔离结构的半导体器件和防止沟槽隔离结构的半导体器件，从而防止晶体管的隆起现象和反向窄宽度效应提供沟槽隔离方法。在这种沟槽隔离方法中，在半导体衬底的非有源区中形成沟槽。在沟槽的内壁上形成厚度为10至150埃的内壁氧化膜。在内壁氧化膜的表面上形成衬垫。沟槽填充有电介质膜。蚀刻衬垫的一部分，使得氮化硅衬垫的顶端从半导体衬底的表面凹陷。

2. 发明授权

US06537914B1 Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing 有权
标题翻译：集成电路器件隔离方法采用高选择性化学机械抛光
公开(公告)号：US06537914B1
公开(公告)日：2003-03-25
申请号：US09570225
申请日：2000-05-12
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee , Jung-yup Kim , Chang-ki Hong , Ho-kyu Kang
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee , Jung-yup Kim , Chang-ki Hong , Ho-kyu Kang
IPC分类号： H01L21302
CPC分类号： C09G1/02 , C09K3/1463 , H01L21/31053 , H01L21/76224
摘要： Trench isolation methods for integrated circuits may reduce irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. In particular, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO2 group abrasive to form an isolation layer in the trench. The CMP selectivity ratio of a slurry that includes a CeO2 group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.
摘要翻译：用于集成电路的沟槽隔离方法可以通过使用高选择性化学机械抛光（CMP）操作来减少形成隔离层的不规则性。特别地，蚀刻衬底表面以形成沟槽。然后在衬底表面和沟槽中形成绝缘层。绝缘层使用包含CeO 2基团研磨剂的浆料进行化学机械抛光，以在沟槽中形成隔离层。包括CeO 2基研磨剂的浆料的CMP选择比可能足以使基板表面用作CMP停止。结果，可以在衬底表面上保持更一致的抛光水平，这可能导致隔离层中更均匀的厚度。

3. 发明授权

US06331469B1 Trench isolation structure, semiconductor device having the same, and trench isolation method 有权
标题翻译：沟槽隔离结构，具有相同的半导体器件，以及沟槽隔离方法
公开(公告)号：US06331469B1
公开(公告)日：2001-12-18
申请号：US09684822
申请日：2000-10-10
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.
摘要翻译：一种沟槽隔离结构，其通过对沟槽的顶部边缘进行舍入并增加在沟槽的顶部边缘处的氧化量，具有沟槽隔离结构的半导体器件和防止沟槽隔离结构的半导体器件，从而防止晶体管的隆起现象和反向窄宽度效应提供沟槽隔离方法。在这种沟槽隔离方法中，在半导体衬底的非有源区中形成沟槽。在沟槽的内壁上形成厚度为10至150埃的内壁氧化膜。在内壁氧化膜的表面上形成衬垫。沟槽填充有电介质膜。蚀刻衬垫的一部分，使得氮化硅衬垫的顶端从半导体衬底的表面凹陷。

4. 发明授权

US5858858A Annealing methods for forming isolation trenches 失效
标题翻译：用于形成隔离沟的退火方法
公开(公告)号：US5858858A
公开(公告)日：1999-01-12
申请号：US729453
申请日：1996-10-11
申请人： Tai-su Park , Moon-han Park , Yu-gyun Shin , Han-sin Lee
发明人： Tai-su Park , Moon-han Park , Yu-gyun Shin , Han-sin Lee
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： A method for forming a microelectronic structure includes the steps of forming a mask layer on a substrate, forming a trench in the exposed portion of the substrate, forming a layer of an insulating material which fills the trench and covers the mask layer, and annealing the insulating material at a temperature of at least about 1,150.degree. C. The annealing step can be performed for a period of time of about .5 hours to about 8 hours, and the annealing step can be performed in an inert atmosphere.
摘要翻译：一种形成微电子结构的方法包括以下步骤：在衬底上形成掩模层，在衬底的暴露部分形成沟槽，形成填充沟槽并覆盖掩模层的绝缘材料层，并退火绝缘材料在至少约1150℃的温度下进行。退火步骤可以进行约0.5小时至约8小时的时间，退火步骤可以在惰性气氛中进行。

5. 发明授权

US06717231B2 Trench isolation regions having recess-inhibiting layers therein that protect against overetching 失效
标题翻译：沟槽隔离区域在其中具有防止过蚀刻的凹陷抑制层
公开(公告)号：US06717231B2
公开(公告)日：2004-04-06
申请号：US10224017
申请日：2002-08-20
申请人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
发明人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.
摘要翻译：形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。掩模层可以包括氮化硅。然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。接下来，在凹陷抑制层上形成应力消除层。该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。然后用沟槽隔离层填充沟槽。然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。

6. 发明授权

US06482715B2 Method of forming shallow trench isolation layer in semiconductor device 有权
公开(公告)号：US06482715B2
公开(公告)日：2002-11-19
申请号：US09927340
申请日：2001-08-13
申请人： Tai-su Park , Ho-kyu Kang , Dong-ho Ahn , Moon-han Park
发明人： Tai-su Park , Ho-kyu Kang , Dong-ho Ahn , Moon-han Park
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.

7. 发明授权

US06461937B1 Methods of forming trench isolation regions having recess-inhibiting layers therein that protect against overetching 失效
标题翻译：形成其中具有防止过蚀刻的凹陷抑制层的沟槽隔离区的方法
公开(公告)号：US06461937B1
公开(公告)日：2002-10-08
申请号：US09479442
申请日：2000-01-07
申请人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
发明人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.
摘要翻译：形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。掩模层可以包括氮化硅。然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。接下来，在凹陷抑制层上形成应力消除层。该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。然后用沟槽隔离层填充沟槽。然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。

8. 发明申请

US20060183296A1 Isolation method for semiconductor device 审中-公开
公开(公告)号：US20060183296A1
公开(公告)日：2006-08-17
申请号：US11398536
申请日：2006-04-06
申请人： Jae-yoon Yoo , Moon-han Park , Dong-ho Ahn , Sug-hun Hong , Kyung-won Park , Jeong-soo Lee
发明人： Jae-yoon Yoo , Moon-han Park , Dong-ho Ahn , Sug-hun Hong , Kyung-won Park , Jeong-soo Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： An isolation method for a semiconductor device where an insulating mask layer is formed on desired regions of a semiconductor substrate. A trench is formed to a desired depth in the semiconductor substrate using the insulating mask layer as a mask. An oxide layer is formed on the insulating mask layer and on the sidewall of the trench. A trench liner layer is formed on the oxide layer. An insulating filler layer is formed in the trench in the semiconductor substrate, on which the trench liner layer is formed, so as to fill the trench. The insulating mask layer is removed. According to the isolation method for a semiconductor device, it is possible to reduce dents from occurring along the edge of the trench, reduce a bird's beak type oxide layer from occurring at an interface between the insulating mask layers, decrease the leakage current, or improve the electrical characteristics, such as threshold voltage.

9. 发明授权

US06624041B2 Method for forming trench type isolation film using annealing 失效
标题翻译：使用退火形成沟槽型隔离膜的方法
公开(公告)号：US06624041B2
公开(公告)日：2003-09-23
申请号：US09316029
申请日：1999-05-21
申请人： Soo-jin Hong , Moon-han Park
发明人： Soo-jin Hong , Moon-han Park
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/823481
摘要： A method for forming a trench type isolation film comprises filling a trench with a composite film, flattening the resultant, and annealing the flattened resultant before a gate oxide film is formed. The annealing diffuses out any contaminant existing in an area near and/or contacting the trench on a surface between a semiconductor substrate and a pad oxide film. Therefore, it is possible to prevent the portion of the gate oxide film which is near the trench from becoming thinner than other portions. Accordingly, it is possible to prevent the characteristic of the gate oxide film from deteriorating. In particular, it is possible to prevent a break down voltage from being lowered.
摘要翻译：用于形成沟槽型隔离膜的方法包括用复合膜填充沟槽，使所得的产品平坦化，并且在形成栅极氧化膜之前使扁平化的结果退火。退火在半导体衬底和衬垫氧化物膜之间的表面上扩散存在于接近和/或接触沟槽的区域中的任何污染物。因此，可以防止沟槽附近的栅极氧化膜的部分变得比其他部分薄。因此，可以防止栅极氧化膜的特性劣化。特别地，可以防止分解电压降低。

10. 发明授权

US5728620A Isolation method of semiconductor device 失效
标题翻译：半导体器件的隔离方法
公开(公告)号：US5728620A
公开(公告)日：1998-03-17
申请号：US591826
申请日：1996-01-25
申请人： Moon-han Park
发明人： Moon-han Park
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/76202
摘要： A device isolation method divides a semiconductor substrate into active and inactive regions. A first device isolation layer is formed in a first inactive region using a trench isolation method. Then, local oxidation is used to form a second device isolation layer in a second inactive region which is wider than the first. A dishing phenomenon (generated during CMP processing) is eliminated, and proper device isolation is realized without exposing the active region.
摘要翻译：器件隔离方法将半导体衬底划分成活性和非活性区域。使用沟槽隔离方法在第一非活性区域中形成第一器件隔离层。然后，使用局部氧化在第二非活性区域中形成第二器件隔离层，其比第一非区域宽。消除了凹陷现象（在CMP处理期间产生），并且在不暴露有源区的情况下实现适当的器件隔离。

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