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1. 发明授权

US06232635B1 Method to fabricate a high coupling flash cell with less silicide seam problem 有权
标题翻译：制造具有较少硅化物接缝问题的高耦合闪存单元的方法
公开(公告)号：US06232635B1
公开(公告)日：2001-05-15
申请号：US09543991
申请日：2000-04-06
申请人： Larry Yu Wang , Steven C. Avanzino , Jeffrey A. Shields , Stephen Keetai Park
发明人： Larry Yu Wang , Steven C. Avanzino , Jeffrey A. Shields , Stephen Keetai Park
IPC分类号： H01L291788
CPC分类号： H01L27/11521 , H01L27/115
摘要： An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer on a silicon substrate, forming an oxide on the isolation formation layer, growing a tunnel oxide layer thereon, depositing a first poly silicon layer, masking and etching the first poly silicon layer, depositing a second poly silicon layer and performing a blanket etch back step, forming an oxide/nitride/oxide layer forming a third poly-silicon layer and depositing a silicide layer thereon.
摘要翻译：制造半导体闪存单元的制品和方法。该方法包括在硅衬底上制造隔离层，在隔离层上形成氧化物，在其上生长隧道氧化物层，沉积第一多晶硅层，掩蔽和蚀刻第一多晶硅层，沉积第二多晶硅层并进行覆盖层回蚀步骤，形成形成第三多晶硅层的氧化物/氮化物/氧化物层并在其上沉积硅化物层。

2. 发明授权

US06410443B1 Method for removing semiconductor ARC using ARC CMP buffing 有权
标题翻译：使用ARC CMP抛光去除半导体ARC的方法
公开(公告)号：US06410443B1
公开(公告)日：2002-06-25
申请号：US09507810
申请日：2000-02-22
申请人： Steven C. Avanzino , Stephen Keetai Park , Kashmir S. Sahota , David H. Matsumoto , Mark Ramsbey
发明人： Steven C. Avanzino , Stephen Keetai Park , Kashmir S. Sahota , David H. Matsumoto , Mark Ramsbey
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01L21/31053 , H01L2924/3011
摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten conductive contacts formed therein. In one embodiment, a chemical-mechanical polishing (CMP) process with non-oxidizer containing slurry is used to selectively remove the ARC layer at a rate which is significantly faster than the removal rates of the dielectric layer or the tungsten contacts. Further, an ARC CMP buffing process is used with a soft buffing pad in the CMP process to buff the dielectric layer and tungsten contacts during the ARC layer removal.
摘要翻译：本发明提供一种用于在基板表面上从电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨导电触头。在一个实施例中，使用含有非氧化剂的浆料的化学 - 机械抛光（CMP）工艺以比电介质层或钨接触的去除速度显着更快的速率选择性地去除ARC层。此外，ARC CMP抛光工艺与CMP抛光垫一起使用，以在ARC层去除期间抛光电介质层和钨触点。

3. 发明授权

US06682978B1 Integrated circuit having increased gate coupling capacitance 有权
标题翻译：具有增加的栅极耦合电容的集成电路
公开(公告)号：US06682978B1
公开(公告)日：2004-01-27
申请号：US09504087
申请日：2000-02-15
申请人： Stephen Keetai Park , Steven C. Avanzino
发明人： Stephen Keetai Park , Steven C. Avanzino
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： The present invention is directed to an integrated circuit having an increased gate coupling capacitance. The integrated circuit includes a substrate having a surface, the substrate having a trench extending below the surface. A trench fill material is disposed in the trench and has a portion extending above the surface. A first conductive layer is adjacent the trench fill material and has a portion extending over the portion of the insulative material. An insulative layer is adjacent the first conductive layer and a second conductive layer is adjacent the insulative layer. The present invention further is directed to a method of fabricating an integrated circuit on a substrate including the steps of forming a trench in the substrate, the trench extending below a surface of the substrate; providing a trench fill material in the trench such that the trench fill material extends above the surface of the substrate; and providing a first conductive layer over at least a portion of the trench fill material.
摘要翻译：本发明涉及具有增加的栅极耦合电容的集成电路。集成电路包括具有表面的衬底，衬底具有在表面下方延伸的沟槽。沟槽填充材料设置在沟槽中并且具有在表面上方延伸的部分。第一导电层与沟槽填充材料相邻并且具有在绝缘材料的一部分上延伸的部分。绝缘层与第一导电层相邻，第二导电层与绝缘层相邻。本发明还涉及一种在衬底上制造集成电路的方法，包括以下步骤：在衬底中形成沟槽，沟槽延伸到衬底的表面下方; 在所述沟槽中提供沟槽填充材料，使得所述沟槽填充材料在所述衬底的表面上方延伸; 以及在所述沟槽填充材料的至少一部分上提供第一导电层。

4. 发明授权

US06265273B1 Method of forming rectangular shaped spacers 有权
标题翻译：形成矩形隔片的方法
公开(公告)号：US06265273B1
公开(公告)日：2001-07-24
申请号：US09359502
申请日：1999-07-23
申请人： Steven C. Avanzino , Stephen Keetai Park , Bharath Rangarajan , Jeffrey A. Shields , Larry Yu Wang , Guarionex Morales
发明人： Steven C. Avanzino , Stephen Keetai Park , Bharath Rangarajan , Jeffrey A. Shields , Larry Yu Wang , Guarionex Morales
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/31116
摘要： A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.
摘要翻译：本文公开了一种在集成电路中形成间隔物的方法。该方法包括在半导体衬底上提供栅极结构，在栅极结构的侧面附近沉积间隔物材料，并蚀刻间隔物材料以形成间隔物。间隔物具有暴露于直接溅射的最小表面积。

5. 发明授权

US07157795B1 Composite tantalum nitride/tantalum copper capping layer 有权
标题翻译：复合氮化钽/钽铜覆盖层
公开(公告)号：US07157795B1
公开(公告)日：2007-01-02
申请号：US10934511
申请日：2004-09-07
申请人： Darrell M. Erb , Steven C. Avanzino , Christy Mei-Chu Woo
发明人： Darrell M. Erb , Steven C. Avanzino , Christy Mei-Chu Woo
IPC分类号： H01L23/48
CPC分类号： H01L21/2855 , H01L21/76843 , H01L21/76846 , H01L21/76849 , Y10S438/927
摘要： Electromigration and stress migration of Cu interconnects are significantly reduced by forming a composite capping layer comprising a layer of tantalum nitride on the upper surface of the inlaid Cu and a layer of α-Ta on the titanium nitride layer. Embodiments include forming a recess in an upper surface of an upper surface of Cu inlaid in a dielectric layer, depositing a layer of titanium nitride of a thickness of 20 Å to 100 Å and then depositing a layer of α-Ta at a thickness of 200 Å to 500 Å.
摘要翻译：通过在镶嵌Cu的上表面上形成包含氮化钽层的复合顶盖层和氮化钛层上的α-Ta层，显着降低了铜互连的电迁移和应力迁移。实施例包括在介电层中嵌入的Cu的上表面的上表面中形成凹陷，沉积厚度为的厚度为的二氧化钛层，然后沉积厚度为200埃的α-Ta层 Å至500Å。

6. 发明授权

US07148144B1 Method of forming copper sulfide layer over substrate 有权
标题翻译：在基材上形成硫化铜层的方法
公开(公告)号：US07148144B1
公开(公告)日：2006-12-12
申请号：US10939897
申请日：2004-09-13
申请人： Steven C. Avanzino
发明人： Steven C. Avanzino
IPC分类号： H01L21/44
CPC分类号： C23C16/18 , C01G3/12 , C23C16/0218 , C23C16/305
摘要： Methods of forming copper sulfide regions or layers over a substrate are disclosed. The copper sulfide regions or layers are formed by contacting a sulfide compound with a substrate containing at least copper and contacting a copper vapor precursor with the substrate to form the copper sulfide layer. Methods of making a memory devices/cells containing a copper sulfide layer, methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.
摘要翻译：公开了在衬底上形成硫化铜区域或层的方法。通过使硫化物化合物与至少含有铜的基材接触并使铜蒸气前体与基材接触而形成硫化铜层而形成硫化铜区域。还公开了制造含有硫化铜层的存储器件/单元的方法，使用存储器件/单元的方法，以及诸如包含存储器件/单元的计算机的器件。

7. 发明授权

US07011762B1 Metal bridging monitor for etch and CMP endpoint detection 失效
标题翻译：用于蚀刻和CMP端点检测的金属桥接监视器
公开(公告)号：US07011762B1
公开(公告)日：2006-03-14
申请号：US10419534
申请日：2003-04-21
申请人： Christopher F. Lyons , Ramkumar Subramanian , Steven C. Avanzino
发明人： Christopher F. Lyons , Ramkumar Subramanian , Steven C. Avanzino
IPC分类号： C23F1/00 , G01R31/00
CPC分类号： H01L21/3212 , H01L21/32051 , H01L21/32136 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. Another aspect of the present relates to a system and method for monitoring a subtractive metallization process in real time in order to effectuate an immediate response in the on-going process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.
摘要翻译：本发明的一个方面涉及包含半导体衬底的晶片，在半导体衬底上形成的至少一个金属层和至少一个嵌入在晶片内和晶片中的至少一个的电传感器，以便于金属的实时监测当它通过减色金属化过程进行时。本发明的另一方面涉及一种用于实时监测减色金属化过程以便在持续过程中实现立即响应的系统和方法。该系统包含晶片，该晶片包括形成在半导体衬底上的至少一个金属层，与晶片接触的至少一个电传感器，其可操作以检测和传输与晶片相关的电活动;以及电测量站，可操作以处理电活动从电传感器检测和接收，用于实时监测减色金属化处理。

8. 发明授权

US06562185B2 Wafer based temperature sensors for characterizing chemical mechanical polishing processes 有权
标题翻译：用于表征化学机械抛光工艺的基于晶圆的温度传感器
公开(公告)号：US06562185B2
公开(公告)日：2003-05-13
申请号：US09955552
申请日：2001-09-18
申请人： Steven C. Avanzino , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
发明人： Steven C. Avanzino , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： B24B3700
CPC分类号： B24B37/015
摘要： A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer that has a metal, polysilicon, and/or dielectric layer and/or substrate and a temperature sensor located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a temperature monitoring system that can read the wafer temperature from the temperature sensors and that can analyze the wafer temperature to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer temperature and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer temperature as related to parameters like polishing time, pressure, speed, slurry properties and wafer/metal layer properties. Such characterization can be employed, for example, to better understand a CMP process, to facilitate initializing subsequent chemical mechanical polishing processes and/or apparatus and/or to control such chemical mechanical polishing processes and/or apparatus by monitoring and/or controlling wafer temperature.
摘要翻译：提供了表征化学机械抛光工艺的系统。该系统包括具有位于金属，多晶硅和/或电介质层和/或衬底中和/或上的金属，多晶硅和/或电介质层和/或衬底和温度传感器的晶片。该系统还包括一个温度监控系统，可以从温度传感器读取晶圆温度，并且可以分析晶圆温度以表征化学机械抛光过程。这种表征包括产生关于晶片温度和抛光速率之间的关系的信息，抛光均匀性和在抛光期间引入缺陷。这些关系与晶片温度相关，如与抛光时间，压力，速度，浆料性质和晶片/金属层性质等参数相关。可以采用这种表征，例如，更好地理解CMP工艺，以便于初始化随后的化学机械抛光工艺和/或设备和/或通过监测和/或控制晶片温度来控制这种化学机械抛光工艺和/或设备。

9. 发明授权

US06530997B1 Use of gaseous silicon hydrides as a reducing agent to remove re-sputtered silicon oxide 有权
标题翻译：使用气态氢化硅作为还原剂去除重新溅射的氧化硅
公开(公告)号：US06530997B1
公开(公告)日：2003-03-11
申请号：US09543484
申请日：2000-04-06
申请人： Steven C. Avanzino , Larry Yu Wang
发明人： Steven C. Avanzino , Larry Yu Wang
IPC分类号： B08B704
CPC分类号： C23C14/022
摘要： A method and article of manufacture of a semiconductor device having a cleaned source/drain surface and substantially uniform cobalt silicide deposited thereon. The method of the invention includes a precursor conventional step of an argon ion pre-sputter step which generally cleans the semiconductor device surfaces but ensures a resputtering of SiO2 to form SiOx species deposits on the source/drain surface of the device. An in situ treatment using silicon hydride species causes reduction of the SiOx species leaving a cleaned residual silicon which can accept a cobalt deposition to form a desired cobalt silicide layer on the source/drain surface.
摘要翻译：具有清洁的源极/漏极表面和沉积在其上的基本均匀的硅化钴的半导体器件的方法和制品。本发明的方法包括氩离子预溅射步骤的前体常规步骤，其通常清洁半导体器件表面，但是确保SiO 2的再溅射以在器件的源极/漏极表面上形成SiO x物质沉积物。使用硅氢化物物质的原位处理导致SiO x物质的还原，留下清洁的剩余硅，其可以接受钴沉积以在源极/漏极表面上形成期望的钴硅化物层。

10. 发明授权

US06469385B1 Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers 有权
标题翻译：集成电路与介质扩散阻挡层形成在互连和层间电介质层之间
公开(公告)号：US06469385B1
公开(公告)日：2002-10-22
申请号：US09874175
申请日：2001-06-04
申请人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
发明人： Steven C. Avanzino , Pin-Chin Connie Wang , Minh Van Ngo
IPC分类号： H01L23522
CPC分类号： H01L23/5329 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76841 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable of being changed into a barrier dielectric material. The dielectric layer around the opening is changed into the barrier dielectric material and the conductor core material is deposited to fill the opening. The conductor core is processed to form a channel for the integrated circuit.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。形成在半导体衬底上的电介质层具有设置在其中的开口。电介质层是能够改变为阻挡介电材料的非阻挡介电材料。开口周围的电介质层变成阻挡电介质材料，并且沉积导体芯材以填充开口。处理导体芯以形成用于集成电路的通道。

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