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1. 发明授权

US06410443B1 Method for removing semiconductor ARC using ARC CMP buffing 有权
标题翻译：使用ARC CMP抛光去除半导体ARC的方法
公开(公告)号：US06410443B1
公开(公告)日：2002-06-25
申请号：US09507810
申请日：2000-02-22
申请人： Steven C. Avanzino , Stephen Keetai Park , Kashmir S. Sahota , David H. Matsumoto , Mark Ramsbey
发明人： Steven C. Avanzino , Stephen Keetai Park , Kashmir S. Sahota , David H. Matsumoto , Mark Ramsbey
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01L21/31053 , H01L2924/3011
摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten conductive contacts formed therein. In one embodiment, a chemical-mechanical polishing (CMP) process with non-oxidizer containing slurry is used to selectively remove the ARC layer at a rate which is significantly faster than the removal rates of the dielectric layer or the tungsten contacts. Further, an ARC CMP buffing process is used with a soft buffing pad in the CMP process to buff the dielectric layer and tungsten contacts during the ARC layer removal.
摘要翻译：本发明提供一种用于在基板表面上从电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨导电触头。在一个实施例中，使用含有非氧化剂的浆料的化学 - 机械抛光（CMP）工艺以比电介质层或钨接触的去除速度显着更快的速率选择性地去除ARC层。此外，ARC CMP抛光工艺与CMP抛光垫一起使用，以在ARC层去除期间抛光电介质层和钨触点。

2. 发明授权

US06720264B2 Prevention of precipitation defects on copper interconnects during CMP by use of solutions containing organic compounds with silica adsorption and copper corrosion inhibiting properties 有权
标题翻译：通过使用含有二氧化硅吸附的有机化合物和铜腐蚀抑制性能的溶液，在CMP期间防止铜互连上的沉淀缺陷
公开(公告)号：US06720264B2
公开(公告)日：2004-04-13
申请号：US09749191
申请日：2000-12-26
申请人： Kashmir S. Sahota , Diana M. Schonauer , Johannes F. Groschopf , Gerd F. C. Marxsen , Steven C. Avanzino
发明人： Kashmir S. Sahota , Diana M. Schonauer , Johannes F. Groschopf , Gerd F. C. Marxsen , Steven C. Avanzino
IPC分类号： H01L21302
CPC分类号： C09K3/1463 , C09G1/02 , H01L21/3212
摘要： A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining. The organic additive is chosen from a class of compounds which form multiple strong adsorbant bonds to the surface of silica or copper, which provide a high degree of surface coverage onto the reactive species, thereby occupying potential reaction sites, and which are sized to sterically hinder the collisions between two reactant molecules which result in new bond formation. The organic additive-containing slurry cain be utilized throughout the entire polish time. Alternatively, a slurry not containing the organic additive can be utilized for a first portion of the polish, and a slurry containing the organic additive or a polishing solution containing the organic additive can be utilized for a second portion of the polish.
摘要翻译：在铜金属化期间用于化学机械抛光（CMP）的Ta阻挡浆料包含抑制沉淀物形成和铜污染的有机添加剂。有机添加剂选自一类化合物，其形成与二氧化硅或铜的表面的多个强吸附剂键，其在反应性物质上提供高度的表面覆盖度，从而占据潜在的反应位点，并且它们的大小适于空间阻碍两个反应物分子之间的碰撞导致新的键形成。在整个抛光时间内可以使用含有机添加剂的浆料。或者，不含有机添加剂的浆料可用于抛光剂的第一部分，并且含有有机添加剂的浆料或含有有机添加剂的抛光溶液可用于第二部分抛光剂。

3. 发明授权

US5665199A Methodology for developing product-specific interlayer dielectric polish processes 失效
标题翻译：开发产品特定层间电介质抛光工艺的方法
公开(公告)号：US5665199A
公开(公告)日：1997-09-09
申请号：US493972
申请日：1995-06-23
申请人： Kashmir S. Sahota , Steven C. Avanzino
发明人： Kashmir S. Sahota , Steven C. Avanzino
IPC分类号： H01L21/3105 , H01L21/66 , H01L21/306
CPC分类号： H01L22/20 , H01L21/31053
摘要： A method for developing and characterizing a polish process for polishing an interlayer dielectric (ILD) layer for a specific product or a specific patterned metal layer is provided. A statistically-based model for ILD planarization by chemical mechanical polish (CMP) is used as a guide to determine, in an empirical manner, the proper amount of ILD polishing that will be required to planarize an ILD layer. The statistically-based model also shows the resulting ILD thicknesses to be expected. By relating the blank test wafer polished amount to the maximum amount of oxide removed from the field areas in the die and the total indicated range across the die, the ILD deposition thickness can be adjusted to attain the desired planarized ILD thickness. The attainment of local planarity, however, must be confirmed by an independent measurement technique. The polish process development methodology is extendible with respect to minimum interconnect feature size. This polish process development methodology can also be applied to products requiring multiple planarizations for multiple levels of interconnects.
摘要翻译：提供了用于开发和表征用于抛光特定产品或特定图案化金属层的层间电介质（ILD）层的抛光工艺的方法。通过化学机械抛光（CMP）的ILD平坦化的统计学模型被用作指导，以经验方式确定平面化ILD层所需的适当量的ILD抛光。基于统计学的模型还显示了预期的ILD厚度。通过将空白测试晶片抛光量与从模具中的场区域去除的氧化物的最大量和跨模具的总指示范围相关联，可以调节ILD沉积厚度以获得期望的平坦化ILD厚度。然而，实现局部平面性必须通过独立的测量技术来确认。抛光过程开发方法在最小互连特征尺寸方面是可扩展的。这种抛光过程开发方法也可以应用于需要多层次互连的多平面化的产品。

4. 发明授权

US06699785B2 Conductor abrasiveless chemical-mechanical polishing in integrated circuit interconnects 失效
标题翻译：导体无接触化学机械抛光在集成电路互连
公开(公告)号：US06699785B2
公开(公告)日：2004-03-02
申请号：US10375219
申请日：2003-02-26
申请人： Kai Yang , Kashmir S. Sahota , Steven C. Avanzino
发明人： Kai Yang , Kashmir S. Sahota , Steven C. Avanzino
IPC分类号： H01L214763
CPC分类号： H01L21/3212 , B24B7/228 , B24B21/04 , H01L21/7684
摘要： A manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. By using a polishing solution having a high selectivity from the conductor core to the barrier layer in conjunction with a grooved polyurethane polish pad, a very thin barrier layer may be used without the conductor core and dielectric layer being subject to erosion and the conductor core being subject to dishing.
摘要翻译：提供具有半导体器件的半导体衬底的制造方法。在半导体衬底上形成器件电介质层。器件电介质层上的沟道电介质层具有形成在其中的开口。屏障层对通道开口进行排列。导体芯填充阻挡层上的开口。通过使用具有从导体芯到阻挡层的高选择性的抛光溶液与凹槽聚氨酯抛光垫结合，可以使用非常薄的阻挡层，而不会导体芯和介电层受到侵蚀，并且导体芯是受到困扰。

5. 发明授权

US06184141B2 Method for multiple phase polishing of a conductive layer in a semidonductor wafer 有权
标题翻译：半导体晶片中导电层的多相抛光方法
公开(公告)号：US06184141B2
公开(公告)日：2001-02-06
申请号：US09198369
申请日：1998-11-24
申请人： Steven C. Avanzino , Kashmir S. Sahota , Gerd Marxsen
发明人： Steven C. Avanzino , Kashmir S. Sahota , Gerd Marxsen
IPC分类号： H01L2100
CPC分类号： H01L21/3212
摘要： A method of planarizing a copper containing conductive layer of a semiconductor wafer forms a blanketing copper containing layer within and upon a patterned substrate layer. Chemical mechanical polish (CMP) planarizing is performed on the copper containing layer at a relatively fast rate of removal until most of the layer is removed. The remaining portion of the layer is then CMP planarized at a second rate of removal, which is slower than the first rate of removal, until the copper containing layer is substantially completely removed and a barrier layer underlying the copper containing layer is reached. The multiple phase planarization of the copper containing layer avoids excessive dishing and pattern erosion while maintaining high throughput and uniform removal.
摘要翻译：平面化半导体晶片的含铜导电层的方法在图案化的衬底层的内部和之上形成覆盖铜的层。化学机械抛光（CMP）平面化在含铜层上以相对较快的去除速率进行，直到大部分层被去除。然后将层的剩余部分以第二除去速率平坦化，其比第一脱除速率慢，直到基本上完全除去含铜层，并且到达含铜层下面的阻挡层。含铜层的多相平面化避免了过度的凹陷和图案侵蚀，同时保持了高产量和均匀的去除。

6. 发明授权

US06503418B2 Ta barrier slurry containing an organic additive 失效
标题翻译：含有有机添加剂的Ta阻隔浆料
公开(公告)号：US06503418B2
公开(公告)日：2003-01-07
申请号：US09434146
申请日：1999-11-04
申请人： Kashmir S. Sahota , Diana M. Schonauer , Steven C. Avanzino
发明人： Kashmir S. Sahota , Diana M. Schonauer , Steven C. Avanzino
IPC分类号： C09K1300
CPC分类号： C09K3/1463
摘要： A Ta barrier slurry for Chemical-Mechanical Polishing (CMP) during copper metallization contains an organic additive which suppresses formation of precipitates and copper staining. The organic additive is chosen from a class of compounds which form multiple strong adsorbant bonds to the surface of silica or copper, which provide a high degree of surface coverage onto the reactive species, thereby occupying potential reaction sites, and which are sized to sterically hinder the collisions between two reactant molecules which result in new bond formation
摘要翻译：在铜金属化期间用于化学机械抛光（CMP）的Ta阻挡浆料包含抑制沉淀物形成和铜污染的有机添加剂。有机添加剂选自一类化合物，其形成与二氧化硅或铜的表面的多个强吸附剂键，其在反应性物质上提供高度的表面覆盖度，从而占据潜在的反应位点，并且它们的大小适于空间阻碍两个反应物分子之间的碰撞导致新的键形成

7. 发明授权

US06413869B1 Dielectric protected chemical-mechanical polishing in integrated circuit interconnects 失效
标题翻译：集成电路互连中的介质保护化学机械抛光
公开(公告)号：US06413869B1
公开(公告)日：2002-07-02
申请号：US09877688
申请日：2001-06-08
申请人： Krishnashree Achuthan , Steven C. Avanzino , Kashmir S. Sahota
发明人： Krishnashree Achuthan , Steven C. Avanzino , Kashmir S. Sahota
IPC分类号： H01L21302
CPC分类号： H01L21/02074 , C09G1/02 , H01L21/3212 , H01L21/7684
摘要： A method is provided for manufacturing an integrated circuit having a semiconductor substrate with a semiconductor device. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening and conductor core is deposited to fill the channel opening over the barrier layer. By using a polishing solution having a dielectric protective characteristic, chemical-mechanical polishing of the conductor core and the barrier layer with the surface of the dielectric layer stops at the surface of the dielectric layer after planarization.
摘要翻译：提供了一种用于制造具有半导体器件的半导体衬底的集成电路的方法。在半导体衬底上形成电介质层，并在电介质层中形成开口。沉积阻挡层以对开口进行排列，并且沉积导体芯以填充阻挡层上的通道开口。通过使用具有介电保护特性的抛光溶液，在平坦化之后，介电层表面的导体芯和阻挡层的化学机械抛光停止在介电层的表面。

8. 发明授权

US06232635B1 Method to fabricate a high coupling flash cell with less silicide seam problem 有权
标题翻译：制造具有较少硅化物接缝问题的高耦合闪存单元的方法
公开(公告)号：US06232635B1
公开(公告)日：2001-05-15
申请号：US09543991
申请日：2000-04-06
申请人： Larry Yu Wang , Steven C. Avanzino , Jeffrey A. Shields , Stephen Keetai Park
发明人： Larry Yu Wang , Steven C. Avanzino , Jeffrey A. Shields , Stephen Keetai Park
IPC分类号： H01L291788
CPC分类号： H01L27/11521 , H01L27/115
摘要： An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer on a silicon substrate, forming an oxide on the isolation formation layer, growing a tunnel oxide layer thereon, depositing a first poly silicon layer, masking and etching the first poly silicon layer, depositing a second poly silicon layer and performing a blanket etch back step, forming an oxide/nitride/oxide layer forming a third poly-silicon layer and depositing a silicide layer thereon.
摘要翻译：制造半导体闪存单元的制品和方法。该方法包括在硅衬底上制造隔离层，在隔离层上形成氧化物，在其上生长隧道氧化物层，沉积第一多晶硅层，掩蔽和蚀刻第一多晶硅层，沉积第二多晶硅层并进行覆盖层回蚀步骤，形成形成第三多晶硅层的氧化物/氮化物/氧化物层并在其上沉积硅化物层。

9. 发明授权

US06682978B1 Integrated circuit having increased gate coupling capacitance 有权
标题翻译：具有增加的栅极耦合电容的集成电路
公开(公告)号：US06682978B1
公开(公告)日：2004-01-27
申请号：US09504087
申请日：2000-02-15
申请人： Stephen Keetai Park , Steven C. Avanzino
发明人： Stephen Keetai Park , Steven C. Avanzino
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： The present invention is directed to an integrated circuit having an increased gate coupling capacitance. The integrated circuit includes a substrate having a surface, the substrate having a trench extending below the surface. A trench fill material is disposed in the trench and has a portion extending above the surface. A first conductive layer is adjacent the trench fill material and has a portion extending over the portion of the insulative material. An insulative layer is adjacent the first conductive layer and a second conductive layer is adjacent the insulative layer. The present invention further is directed to a method of fabricating an integrated circuit on a substrate including the steps of forming a trench in the substrate, the trench extending below a surface of the substrate; providing a trench fill material in the trench such that the trench fill material extends above the surface of the substrate; and providing a first conductive layer over at least a portion of the trench fill material.
摘要翻译：本发明涉及具有增加的栅极耦合电容的集成电路。集成电路包括具有表面的衬底，衬底具有在表面下方延伸的沟槽。沟槽填充材料设置在沟槽中并且具有在表面上方延伸的部分。第一导电层与沟槽填充材料相邻并且具有在绝缘材料的一部分上延伸的部分。绝缘层与第一导电层相邻，第二导电层与绝缘层相邻。本发明还涉及一种在衬底上制造集成电路的方法，包括以下步骤：在衬底中形成沟槽，沟槽延伸到衬底的表面下方; 在所述沟槽中提供沟槽填充材料，使得所述沟槽填充材料在所述衬底的表面上方延伸; 以及在所述沟槽填充材料的至少一部分上提供第一导电层。

10. 发明授权

US06265273B1 Method of forming rectangular shaped spacers 有权
标题翻译：形成矩形隔片的方法
公开(公告)号：US06265273B1
公开(公告)日：2001-07-24
申请号：US09359502
申请日：1999-07-23
申请人： Steven C. Avanzino , Stephen Keetai Park , Bharath Rangarajan , Jeffrey A. Shields , Larry Yu Wang , Guarionex Morales
发明人： Steven C. Avanzino , Stephen Keetai Park , Bharath Rangarajan , Jeffrey A. Shields , Larry Yu Wang , Guarionex Morales
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/31116
摘要： A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.
摘要翻译：本文公开了一种在集成电路中形成间隔物的方法。该方法包括在半导体衬底上提供栅极结构，在栅极结构的侧面附近沉积间隔物材料，并蚀刻间隔物材料以形成间隔物。间隔物具有暴露于直接溅射的最小表面积。

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