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1. 发明授权

US06265273B1 Method of forming rectangular shaped spacers 有权
标题翻译：形成矩形隔片的方法
公开(公告)号：US06265273B1
公开(公告)日：2001-07-24
申请号：US09359502
申请日：1999-07-23
申请人： Steven C. Avanzino , Stephen Keetai Park , Bharath Rangarajan , Jeffrey A. Shields , Larry Yu Wang , Guarionex Morales
发明人： Steven C. Avanzino , Stephen Keetai Park , Bharath Rangarajan , Jeffrey A. Shields , Larry Yu Wang , Guarionex Morales
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/31116
摘要： A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.
摘要翻译：本文公开了一种在集成电路中形成间隔物的方法。该方法包括在半导体衬底上提供栅极结构，在栅极结构的侧面附近沉积间隔物材料，并蚀刻间隔物材料以形成间隔物。间隔物具有暴露于直接溅射的最小表面积。

2. 发明授权

US06232635B1 Method to fabricate a high coupling flash cell with less silicide seam problem 有权
标题翻译：制造具有较少硅化物接缝问题的高耦合闪存单元的方法
公开(公告)号：US06232635B1
公开(公告)日：2001-05-15
申请号：US09543991
申请日：2000-04-06
申请人： Larry Yu Wang , Steven C. Avanzino , Jeffrey A. Shields , Stephen Keetai Park
发明人： Larry Yu Wang , Steven C. Avanzino , Jeffrey A. Shields , Stephen Keetai Park
IPC分类号： H01L291788
CPC分类号： H01L27/11521 , H01L27/115
摘要： An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer on a silicon substrate, forming an oxide on the isolation formation layer, growing a tunnel oxide layer thereon, depositing a first poly silicon layer, masking and etching the first poly silicon layer, depositing a second poly silicon layer and performing a blanket etch back step, forming an oxide/nitride/oxide layer forming a third poly-silicon layer and depositing a silicide layer thereon.
摘要翻译：制造半导体闪存单元的制品和方法。该方法包括在硅衬底上制造隔离层，在隔离层上形成氧化物，在其上生长隧道氧化物层，沉积第一多晶硅层，掩蔽和蚀刻第一多晶硅层，沉积第二多晶硅层并进行覆盖层回蚀步骤，形成形成第三多晶硅层的氧化物/氮化物/氧化物层并在其上沉积硅化物层。

3. 发明授权

US06265294B1 Integrated circuit having double bottom anti-reflective coating layer 有权
标题翻译：具有双层防反射涂层的集成电路
公开(公告)号：US06265294B1
公开(公告)日：2001-07-24
申请号：US09373084
申请日：1999-08-12
申请人： Stephen Keetai Park , Guarionex Morales , Bharath Rangarajan , Jeff Shields
发明人： Stephen Keetai Park , Guarionex Morales , Bharath Rangarajan , Jeff Shields
IPC分类号： H01L21425
CPC分类号： H01L23/5329 , H01L21/0276 , H01L21/31144 , H01L21/3144 , H01L21/76829 , H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： A fabrication method reduces the amount of discoloration on interlevel dielectric layers due to anti-reflective coatings (ARC). The invention utilizes a barrier layer, such as, silicon nitride (SiN) that prevents the anti-reflective coating from contacting the interlevel dielectric layer (ILD0). The anti-reflective coating can be silicon oxynitride (SiON) deposited by LPCVD or PECVD.
摘要翻译：制造方法减少了由于抗反射涂层（ARC）引起的层间电介质层上的变色量。本发明利用阻挡层，例如防止抗反射涂层与层间介质层（ILD0）接触的氮化硅（SiN）。抗反射涂层可以是通过LPCVD或PECVD沉积的氮氧化硅（SiON）。

4. 发明授权

US06420104B1 Method of reducing contact size by spacer filling 失效
标题翻译：通过间隔物填充减小接触尺寸的方法
公开(公告)号：US06420104B1
公开(公告)日：2002-07-16
申请号：US09705941
申请日：2000-11-03
申请人： Bharath Rangarajan , Stephen Keetai Park , Guarionex Morales
发明人： Bharath Rangarajan , Stephen Keetai Park , Guarionex Morales
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/76816 , H01L21/76832
摘要： A method of reducing contact size in an integrated circuit includes providing an insulating layer over a semiconductor substrate including a plurality of gate structures, creating an aperture extending through the insulating layer and having side walls, providing a spacer on the side walls of the aperture, and providing a contact in the aperture. The lateral sides of the contact abut the spacer. A contact structure is also disclosed in which a spacer separates a contact from a gate structure to avoid charge gain or loss between the contact and gate structure.
摘要翻译：减小集成电路中的接触尺寸的方法包括在包括多个栅极结构的半导体衬底之上提供绝缘层，形成延伸穿过绝缘层并具有侧壁的孔，在孔的侧壁上提供间隔物，并在孔中提供接触。接触件的侧面靠垫片。还公开了一种接触结构，其中隔离物将接触与栅极结构分离以避免接触和栅极结构之间的电荷增益或损耗。

5. 发明授权

US06410443B1 Method for removing semiconductor ARC using ARC CMP buffing 有权
标题翻译：使用ARC CMP抛光去除半导体ARC的方法
公开(公告)号：US06410443B1
公开(公告)日：2002-06-25
申请号：US09507810
申请日：2000-02-22
申请人： Steven C. Avanzino , Stephen Keetai Park , Kashmir S. Sahota , David H. Matsumoto , Mark Ramsbey
发明人： Steven C. Avanzino , Stephen Keetai Park , Kashmir S. Sahota , David H. Matsumoto , Mark Ramsbey
IPC分类号： H01L21302
CPC分类号： H01L21/76897 , H01L21/31053 , H01L2924/3011
摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten conductive contacts formed therein. In one embodiment, a chemical-mechanical polishing (CMP) process with non-oxidizer containing slurry is used to selectively remove the ARC layer at a rate which is significantly faster than the removal rates of the dielectric layer or the tungsten contacts. Further, an ARC CMP buffing process is used with a soft buffing pad in the CMP process to buff the dielectric layer and tungsten contacts during the ARC layer removal.
摘要翻译：本发明提供一种用于在基板表面上从电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨导电触头。在一个实施例中，使用含有非氧化剂的浆料的化学 - 机械抛光（CMP）工艺以比电介质层或钨接触的去除速度显着更快的速率选择性地去除ARC层。此外，ARC CMP抛光工艺与CMP抛光垫一起使用，以在ARC层去除期间抛光电介质层和钨触点。

6. 发明授权

US06682978B1 Integrated circuit having increased gate coupling capacitance 有权
标题翻译：具有增加的栅极耦合电容的集成电路
公开(公告)号：US06682978B1
公开(公告)日：2004-01-27
申请号：US09504087
申请日：2000-02-15
申请人： Stephen Keetai Park , Steven C. Avanzino
发明人： Stephen Keetai Park , Steven C. Avanzino
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： The present invention is directed to an integrated circuit having an increased gate coupling capacitance. The integrated circuit includes a substrate having a surface, the substrate having a trench extending below the surface. A trench fill material is disposed in the trench and has a portion extending above the surface. A first conductive layer is adjacent the trench fill material and has a portion extending over the portion of the insulative material. An insulative layer is adjacent the first conductive layer and a second conductive layer is adjacent the insulative layer. The present invention further is directed to a method of fabricating an integrated circuit on a substrate including the steps of forming a trench in the substrate, the trench extending below a surface of the substrate; providing a trench fill material in the trench such that the trench fill material extends above the surface of the substrate; and providing a first conductive layer over at least a portion of the trench fill material.
摘要翻译：本发明涉及具有增加的栅极耦合电容的集成电路。集成电路包括具有表面的衬底，衬底具有在表面下方延伸的沟槽。沟槽填充材料设置在沟槽中并且具有在表面上方延伸的部分。第一导电层与沟槽填充材料相邻并且具有在绝缘材料的一部分上延伸的部分。绝缘层与第一导电层相邻，第二导电层与绝缘层相邻。本发明还涉及一种在衬底上制造集成电路的方法，包括以下步骤：在衬底中形成沟槽，沟槽延伸到衬底的表面下方; 在所述沟槽中提供沟槽填充材料，使得所述沟槽填充材料在所述衬底的表面上方延伸; 以及在所述沟槽填充材料的至少一部分上提供第一导电层。

7. 发明授权

US06287917B1 Process for fabricating an MNOS flash memory device 有权
标题翻译：制造MNOS闪存设备的过程
公开(公告)号：US06287917B1
公开(公告)日：2001-09-11
申请号：US09392675
申请日：1999-09-08
申请人： Stephen Keetai Park , Tim Thurgate , Bharath Rangarajan
发明人： Stephen Keetai Park , Tim Thurgate , Bharath Rangarajan
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A process for fabricating an MNOS device includes the steps of forming a hardmask containing at least first and second openings over a core array area of a semiconductor substrate. An angle doping process is carried out to form halo regions in precise locations within the substrate at the edges of the first and second openings in the hardmask. Another doping process is carried out to form buried bit-lines in the substrate using the hardmask as a doping mask. Once the halo regions and the buried bit-lines are formed, the hardmask is removed and a composite dielectric layer is formed overlying the substrate. A gate layer is deposited to overlie the composite dielectric layer, and an etching process is carried out to form a control gate electrode and a charge storage electrode in the MNOS device
摘要翻译：制造MNOS器件的方法包括以下步骤：在半导体衬底的芯阵列区域上形成至少包含第一和第二开口的硬掩模。进行角度掺杂处理以在硬掩模中的第一和第二开口的边缘处在衬底内的精确位置中形成晕圈。进行另一种掺杂工艺以使用硬掩模作为掺杂掩模在衬底中形成掩埋位线。一旦形成了光晕区域和掩埋位线，就去除了硬掩模，并且在衬底上形成复合介电层。沉积栅极层以覆盖复合介电层，并且进行蚀刻处理以在MNOS器件中形成控制栅电极和电荷存储电极

8. 发明授权

US06486506B1 Flash memory with less susceptibility to charge gain and charge loss 有权
标题翻译：闪存对电荷增益和电荷损失的敏感性较小
公开(公告)号：US06486506B1
公开(公告)日：2002-11-26
申请号：US09532293
申请日：2000-03-23
申请人： Stephen Keetai Park , Jeffrey A. Shields
发明人： Stephen Keetai Park , Jeffrey A. Shields
IPC分类号： H01L2972
CPC分类号： H01L27/11521 , H01L23/3192 , H01L23/564 , H01L27/115 , H01L29/42324 , H01L2924/0002 , H01L2924/3025 , H01L2924/00
摘要： An integrated circuit is designed to reduce charge gain and charge loss in a flash memory or flash programmable read-only memory. Charge gain and loss caused by moisture or hydrogen diffusion or alternately small contact-to-floating gate distance is reduced by a capping layer disposed over a gate stack and a base layer of the flash memory. The capping layer includes a buffer layer, a first insulative layer, and a second insulative layer. The etch characteristics of at least the first and second insulative layer differs from an interlevel dielectric to control the dimensions of a contact extending through the interlevel dielectric and the capping layer to the base layer.
摘要翻译：集成电路设计用于减少闪存或闪存可编程只读存储器中的充电增益和电荷损耗。通过设置在闪存的栅极堆叠和基极层上的覆盖层减少由水分或氢扩散引起的电荷增益和损耗，或者交替地小的接触到浮置栅极距离。封盖层包括缓冲层，第一绝缘层和第二绝缘层。至少第一绝缘层和第二绝缘层的蚀刻特性不同于层间电介质，以控制延伸穿过层间电介质和覆盖层到基底层的接触层的尺寸。

9. 发明授权

US06306758B1 Multipurpose graded silicon oxynitride cap layer 有权
标题翻译：多用途分级氮氧化硅盖层
公开(公告)号：US06306758B1
公开(公告)日：2001-10-23
申请号：US09567534
申请日：2000-05-10
申请人： Stephen Keetai Park
发明人： Stephen Keetai Park
IPC分类号： H01L214763
CPC分类号： H01L21/28061 , H01L21/28123 , H01L21/28273
摘要： A graded cap layer that reduces the overall height of a layer stack and provides for increased process control during subsequent patterning of the layer stack, is described with a method of making the same. The graded cap layer is configured to function as a cap layer to prevent an underlying silicide layer from lifting, a barrier layer to prevent the underlying silicide layer from being oxidized during subsequent processes, a stop layer to prevent over-etching during subsequent self-aligned source (SAS) patterning processes, and/or an anti-reflective coating (ARC) to improve the resolution of subsequent patterning processes. The graded cap layer is a relatively thin layer of silicon oxynitride with varying concentrations of nitrogen. The cap layer is deposited in a single chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) chamber.
摘要翻译：通过制造相同的方法来描述降低层堆叠的总体高度并且在随后的层叠图案化期间提供增加的工艺控制的分级盖层。渐变盖层被配置为用作覆盖层以防止下面的硅化物层提升，阻挡层以防止下一个硅化物层在后续工艺期间被氧化，阻止层以防止随后自对准期间的过度蚀刻源（SAS）图案化工艺和/或抗反射涂层（ARC））以提高随后的图案化工艺的分辨率。分级覆盖层是具有不同浓度的氮的相对薄的氮氧化硅层。盖层沉积在单一化学气相沉积（CVD）或等离子体增强化学气相沉积（PECVD）室中。

10. 发明授权

US6100559A Multipurpose graded silicon oxynitride cap layer 有权
标题翻译：多用途分级氮氧化硅盖层
公开(公告)号：US6100559A
公开(公告)日：2000-08-08
申请号：US134525
申请日：1998-08-14
申请人： Stephen Keetai Park
发明人： Stephen Keetai Park
IPC分类号： H01L21/28 , H01L21/331 , H01L21/8222
CPC分类号： H01L21/28061 , H01L21/28123 , H01L21/28273
摘要： A graded cap layer that reduces the overall height of a layer stack and provides for increased process control during subsequent patterning of the layer stack, is described with a method of making the same. The graded cap layer is configured to function as a cap layer to prevent an underlying silicide layer from lifting, a barrier layer to prevent the underlying silicide layer from being oxidized during subsequent processes, a stop layer to prevent over-etching during subsequent self-aligned source (SAS) patterning processes, and/or an anti-reflective coating (ARC) to improve the resolution of subsequent patterning processes. The graded cap layer is a relatively thin layer of silicon oxynitride with varying concentrations of nitrogen. The cap layer is deposited in a single chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) chamber.
摘要翻译：通过制造相同的方法来描述降低层堆叠的总体高度并且在随后的层叠图案化期间提供增加的工艺控制的分级盖层。渐变盖层被配置为用作覆盖层以防止下面的硅化物层提升，阻挡层以防止下一个硅化物层在后续工艺期间被氧化，阻止层以防止随后自对准期间的过度蚀刻源（SAS）图案化工艺和/或抗反射涂层（ARC））以提高随后的图案化工艺的分辨率。分级覆盖层是具有不同浓度的氮的相对薄的氮氧化硅层。盖层沉积在单一化学气相沉积（CVD）或等离子体增强化学气相沉积（PECVD）室中。

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