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1. 发明申请

US20070001217A1 Closed loop CESL high performance CMOS devices 有权
标题翻译：闭环CESL高性能CMOS器件
公开(公告)号：US20070001217A1
公开(公告)日：2007-01-04
申请号：US11170201
申请日：2005-06-29
申请人： Shang-Chih Chen , Shih-Hsieng Huang , Chih-Hao Wang
发明人： Shang-Chih Chen , Shih-Hsieng Huang , Chih-Hao Wang
IPC分类号： H01L29/788
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/6656 , H01L29/7833 , H01L29/7843 , Y10S257/90
摘要： An N-MOS and/or P-MOS device having enhanced performance such as an FET suitable for use in a CMOS circuit. The device comprises both an “L-like” shaped layer or spacer on the side walls of a gate structure as well as a CESL (contact-etch stop layer) that covers the gate structure and surrounding substrate to induce increase tensile stresses in the N-MOS device and increased compressive stresses in the P-MOS device.
摘要翻译：具有增强性能的N-MOS和/或P-MOS器件，例如适用于CMOS电路的FET。该器件包括栅极结构的侧壁上的“L形”形状的层或间隔物以及覆盖栅极结构和周围衬底的CESL（接触蚀刻停止层），以在N中引起增加的拉伸应力 -MOS器件和P-MOS器件中增加的压应力。

2. 发明授权

US07829978B2 Closed loop CESL high performance CMOS device 有权
标题翻译：闭环CESL高性能CMOS器件
公开(公告)号：US07829978B2
公开(公告)日：2010-11-09
申请号：US11170201
申请日：2005-06-29
申请人： Shang-Chih Chen , Shih-Hsieng Huang , Chih-Hao Wang
发明人： Shang-Chih Chen , Shih-Hsieng Huang , Chih-Hao Wang
IPC分类号： H01L23/58
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/6656 , H01L29/7833 , H01L29/7843 , Y10S257/90
摘要： An N-MOS and/or P-MOS device having enhanced performance such as an FET suitable for use in a CMOS circuit. The device comprises both an “L-like” shaped layer or spacer on the side walls of a gate structure as well as a CESL (contact-etch stop layer) that covers the gate structure and surrounding substrate to induce increase tensile stresses in the N-MOS device and increased compressive stresses in the P-MOS device.
摘要翻译：具有增强性能的N-MOS和/或P-MOS器件，例如适用于CMOS电路的FET。该器件包括栅极结构的侧壁上的“L形”形状的层或间隔物以及覆盖栅极结构和周围衬底的CESL（接触蚀刻停止层），以在N中引起增加的拉伸应力 -MOS器件和P-MOS器件中增加的压应力。

3. 发明授权

US07229893B2 Method and apparatus for a semiconductor device with a high-k gate dielectric 有权
标题翻译：具有高k栅极电介质的半导体器件的方法和装置
公开(公告)号：US07229893B2
公开(公告)日：2007-06-12
申请号：US11021269
申请日：2004-12-23
申请人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
发明人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L21/823468 , H01L21/823481 , H01L27/10852 , H01L27/10873 , H01L27/10894
摘要： A process and apparatus for a high gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extends beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.
摘要翻译：描述了一种高栅极介电MOS晶体管的工艺和装置。提供衬底，在衬底上沉积高k栅极电介质材料，在电介质材料上沉积栅极电极层，并且执行构图步骤，其产生电极和电介质的侧壁并去除衬底的一部分。侧壁材料沉积在图案化的栅极电极上，并且在图案化的栅电极和在电介质的底部下方延伸的电介质上形成电介质。在替代实施例中，沟道材料沉积在高k栅极电介质的下方，并且图案化步骤去除高k栅极电介质下方的沟道材料的至少一部分。在替代实施例中，沟道材料是反掺杂的。

4. 发明申请

US20050287759A1 Method and apparatus for a semiconductor device with a high-k gate dielectric 有权
标题翻译：具有高k栅极电介质的半导体器件的方法和装置
公开(公告)号：US20050287759A1
公开(公告)日：2005-12-29
申请号：US11021269
申请日：2004-12-23
申请人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
发明人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
IPC分类号： H01L21/00 , H01L21/8234 , H01L21/8242
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L21/823468 , H01L21/823481 , H01L27/10852 , H01L27/10873 , H01L27/10894
摘要： A process and apparatus for a high gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extends beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.
摘要翻译：描述了一种高栅极介电MOS晶体管的工艺和装置。提供衬底，在衬底上沉积高k栅极电介质材料，在电介质材料上沉积栅极电极层，并且执行构图步骤，其产生电极和电介质的侧壁并去除衬底的一部分。侧壁材料沉积在图案化的栅极电极上，并且在图案化的栅电极和在电介质的底部下方延伸的电介质上形成电介质。在替代实施例中，沟道材料沉积在高k栅极电介质的下方，并且图案化步骤去除高k栅极电介质下方的沟道材料的至少一部分。在替代实施例中，沟道材料是反掺杂的。

5. 发明申请

US20050035345A1 Semiconductor device with high-k gate dielectric 有权
标题翻译：具有高k栅极电介质的半导体器件
公开(公告)号：US20050035345A1
公开(公告)日：2005-02-17
申请号：US10832020
申请日：2004-04-26
申请人： Chun-Chieh Lin , Wen-Chin Lee , Chenming Hu , Shang-Chih Chen , Chih-Hao Wang , Fu-Liang Yang , Yee-Chia Yeo
发明人： Chun-Chieh Lin , Wen-Chin Lee , Chenming Hu , Shang-Chih Chen , Chih-Hao Wang , Fu-Liang Yang , Yee-Chia Yeo
IPC分类号： H01L21/28 , H01L21/8234 , H01L29/51 , H01L29/06
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/823462 , H01L29/513 , H01L29/517 , H01L29/518
摘要： An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.
摘要翻译：集成电路包括衬底，第一晶体管和第二晶体管。第一晶体管具有位于第一栅电极和衬底之间的第一栅电介质部分。第一栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。第一栅介质部分具有第一等效氧化硅厚度。第二晶体管具有位于第二栅电极和衬底之间的第二栅介质部分。第二栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。第二栅介质部分具有第二等效氧化硅厚度。第二等效氧化硅厚度可以不同于第一等效氧化硅厚度。

6. 发明申请

US20120083076A1 Ultra-Shallow Junction MOSFET Having a High-k Gate Dielectric and In-Situ Doped Selective Epitaxy Source/Drain Extensions and a Method of Making Same 有权
标题翻译：具有高k栅介质和原位掺杂选择性外延源/漏极扩展的超浅结结MOSFET及其制作方法
公开(公告)号：US20120083076A1
公开(公告)日：2012-04-05
申请号：US13324592
申请日：2011-12-13
申请人： Chih-Hao Wang , Shang-Chih Chen , Yen-Ping Wang , Hsien-Kuang Chiu , Liang-Gi Yao , Chenming Hu
发明人： Chih-Hao Wang , Shang-Chih Chen , Yen-Ping Wang , Hsien-Kuang Chiu , Liang-Gi Yao , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7833
摘要： A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.
摘要翻译： MOSFET包括在衬底上具有高k栅极电介质的栅极和栅极电介质上的栅极电极。栅极电介质突出超过栅电极。在栅极的任一侧形成具有浅延伸的深源极和漏极。深源和漏极通过选择性原位掺杂外延或通过离子注入形成，并且通过选择性原位掺杂外延形成延伸。延伸部位于与栅极电介质接触的栅极下方。选择栅极电介质的材料和其突出超过栅电极的量，使得外延程序和相关过程不会引起栅极电极和源极/漏极延伸部之间的桥接。描述制造MOSFET的方法。

7. 发明申请

US20090090935A1 High Performance CMOS Device Design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US20090090935A1
公开(公告)日：2009-04-09
申请号：US12330961
申请日：2008-12-09
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L29/78
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

8. 发明授权

US07205186B2 System and method for suppressing oxide formation 有权
标题翻译：抑制氧化物形成的系统和方法
公开(公告)号：US07205186B2
公开(公告)日：2007-04-17
申请号：US11025040
申请日：2004-12-29
申请人： Chih-Hao Wang , Shang-Chih Chen
发明人： Chih-Hao Wang , Shang-Chih Chen
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/0217 , H01L21/28176 , H01L21/28194 , H01L21/28247 , H01L21/3144 , H01L21/3185 , H01L29/4983 , H01L29/513 , H01L29/517 , H01L29/66636 , Y10S438/954
摘要： A system and method for suppressing sub-oxide formation during the manufacturing of semiconductor devices (such as MOSFET transistor) with high-k gate dielectric is disclosed. In one example, the MOSFET transistor includes a gate structure including a high-k gate dielectric and a gate electrode. In this example, the gate structure is covered with a nitride layer that is used to prevent oxygen from entering the structure during processing, yet is sufficiently thin to be effectively transparent to the processing.
摘要翻译：公开了一种用于在制造具有高k栅极电介质的半导体器件（例如MOSFET晶体管）的制造期间抑制次氧化物形成的系统和方法。在一个示例中，MOSFET晶体管包括包括高k栅极电介质和栅电极的栅极结构。在该示例中，栅极结构覆盖有用于在处理期间防止氧气进入结构的氮化物层，但是其足够薄以对加工有效地透明。

9. 发明申请

US20060172480A1 Single metal gate CMOS device design 审中-公开
标题翻译：单金属栅CMOS器件设计
公开(公告)号：US20060172480A1
公开(公告)日：2006-08-03
申请号：US11048877
申请日：2005-02-03
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/8234
CPC分类号： H01L21/823842
摘要： A semiconductor device includes a PMOS transistor formed on a substrate structure. The PMOS transistor includes a source and a drain each including a diffusion region in the substrate structure, a channel region defined between the source and the drain, a gate dielectric over the channel region, and a gate electrode over the gate dielectric. The gate electrode is formed of a material having an n-type work function with respect to the semiconductor substrate and is treated such that a work function of the gate electrode is converted into a mid-gap type or p-type work function with respect to the semiconductor substrate.
摘要翻译：半导体器件包括形成在衬底结构上的PMOS晶体管。 PMOS晶体管包括源极和漏极，每个源极和漏极在衬底结构中包括扩散区域，限定在源极和漏极之间的沟道区域，沟道区域上的栅极电介质，以及栅极电介质上的栅极电极。栅极由相对于半导体衬底具有n型功函数的材料形成，并且被处理为使得栅极的功函数转换为相对于第二栅极的中间间隙型或p型功函数半导体衬底。

10. 发明申请

US20060131675A1 Semiconductor device and method for high-K gate dielectrics 有权
标题翻译：用于高K栅极电介质的半导体器件和方法
公开(公告)号：US20060131675A1
公开(公告)日：2006-06-22
申请号：US11020377
申请日：2004-12-22
申请人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
发明人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
IPC分类号： H01L29/94
CPC分类号： H01L29/517 , H01L21/28194 , H01L21/28202 , H01L29/1054 , H01L29/513 , H01L29/518 , H01L29/78
摘要： A semiconductor device and process including a high-k gate dielectric is described. A substrate is provided, and a high-k gate dielectric material, preferably amorphous HfSiON, is deposited over the substrate. In preferred embodiments, the high-k dielectric material includes nitrogen. In a preferred embodiment, a silicon nitride layer is deposited using jet vapor deposition (JVD) on the high-k dielectric material. When the JVD nitride layer is deposited according to preferred embodiments, the layer has a low density of charge traps, it maintains comparable carrier mobility and provides better EOT compared to oxide or oxynitride. A second nitrogen-containing layer formed between the high-k dielectric and the gate electrode acts as a diffusion barrier. It also reduces problems relating to oxygen vacancy formation in high-k dielectric and therefore minimizes Fermi-level pinning.
摘要翻译：描述了包括高k栅极电介质的半导体器件和工艺。提供衬底，并且在衬底上沉积高k栅介质材料，优选无定形HfSiON。在优选实施例中，高k电介质材料包括氮。在优选实施例中，使用喷射气相沉积（JVD）在高k电介质材料上沉积氮化硅层。当根据优选实施方案沉积JVD氮化物层时，该层具有低密度的电荷陷阱，与氧化物或氧氮化物相比，其维持可比较的载流子迁移率并提供更好的EOT。形成在高k电介质和栅电极之间的第二含氮层用作扩散阻挡层。它还减少了在高k电介质中与氧空位形成有关的问题，从而使费米能级钉扎最小化。

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