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1. 发明授权

US07229893B2 Method and apparatus for a semiconductor device with a high-k gate dielectric 有权
标题翻译：具有高k栅极电介质的半导体器件的方法和装置
公开(公告)号：US07229893B2
公开(公告)日：2007-06-12
申请号：US11021269
申请日：2004-12-23
申请人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
发明人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L21/823468 , H01L21/823481 , H01L27/10852 , H01L27/10873 , H01L27/10894
摘要： A process and apparatus for a high gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extends beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.
摘要翻译：描述了一种高栅极介电MOS晶体管的工艺和装置。提供衬底，在衬底上沉积高k栅极电介质材料，在电介质材料上沉积栅极电极层，并且执行构图步骤，其产生电极和电介质的侧壁并去除衬底的一部分。侧壁材料沉积在图案化的栅极电极上，并且在图案化的栅电极和在电介质的底部下方延伸的电介质上形成电介质。在替代实施例中，沟道材料沉积在高k栅极电介质的下方，并且图案化步骤去除高k栅极电介质下方的沟道材料的至少一部分。在替代实施例中，沟道材料是反掺杂的。

2. 发明申请

US20050287759A1 Method and apparatus for a semiconductor device with a high-k gate dielectric 有权
标题翻译：具有高k栅极电介质的半导体器件的方法和装置
公开(公告)号：US20050287759A1
公开(公告)日：2005-12-29
申请号：US11021269
申请日：2004-12-23
申请人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
发明人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
IPC分类号： H01L21/00 , H01L21/8234 , H01L21/8242
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L21/823468 , H01L21/823481 , H01L27/10852 , H01L27/10873 , H01L27/10894
摘要： A process and apparatus for a high gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extends beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.
摘要翻译：描述了一种高栅极介电MOS晶体管的工艺和装置。提供衬底，在衬底上沉积高k栅极电介质材料，在电介质材料上沉积栅极电极层，并且执行构图步骤，其产生电极和电介质的侧壁并去除衬底的一部分。侧壁材料沉积在图案化的栅极电极上，并且在图案化的栅电极和在电介质的底部下方延伸的电介质上形成电介质。在替代实施例中，沟道材料沉积在高k栅极电介质的下方，并且图案化步骤去除高k栅极电介质下方的沟道材料的至少一部分。在替代实施例中，沟道材料是反掺杂的。

3. 发明授权

US07465972B2 High performance CMOS device design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US07465972B2
公开(公告)日：2008-12-16
申请号：US11115484
申请日：2005-04-27
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L31/62
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

4. 发明申请

US20060131672A1 Nitrogen treatment to improve high-k gate dielectrics 有权
标题翻译：氮处理改善高k栅极电介质
公开(公告)号：US20060131672A1
公开(公告)日：2006-06-22
申请号：US11115932
申请日：2005-04-27
申请人： Chih-Hao Wang , Ta-Wei Wang , Shang-Chih Chen , Ching-Wei Tsai
发明人： Chih-Hao Wang , Ta-Wei Wang , Shang-Chih Chen , Ching-Wei Tsai
IPC分类号： H01L29/94
CPC分类号： H01L21/823462 , H01L21/28202 , H01L21/76829 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A MOSFET having a nitrided gate dielectric and its manufacture are disclosed. The method comprises providing a substrate and depositing a non-high-k dielectric material on the substrate. The non-high-k dielectric comprises two layers. The first layer adjacent the substrate is essentially nitrogen-free, and the second layer includes between about 1015 atoms/cm3 to about 1022 atoms/cm3 nitrogen. The MOSFET further includes a high-k dielectric material on the nitrided, non-high-k dielectric. The high-k dielectric preferably includes HfSiON, ZrSiON, or nitrided Al2O3. Embodiments further include asymmetric manufacturing techniques wherein core and peripheral integrated circuit areas are separately optimized.
摘要翻译：公开了具有氮化栅极电介质的MOSFET及其制造。该方法包括提供衬底并在衬底上沉积非高k电介质材料。非高k电介质包括两层。与衬底相邻的第一层基本上是无氮的，而第二层包含约10 15个原子/ cm 3至约10 22个/ 原子/ cm 3氮气。 MOSFET还包括在氮化的非高k电介质上的高k电介质材料。高k电介质优选包括HfSiON，ZrSiON或氮化的Al 2 O 3 N 3。实施例还包括其中核心和外围集成电路区域被分开优化的不对称制造技术。

5. 发明授权

US07355235B2 Semiconductor device and method for high-k gate dielectrics 有权
标题翻译：用于高k栅极电介质的半导体器件和方法
公开(公告)号：US07355235B2
公开(公告)日：2008-04-08
申请号：US11020377
申请日：2004-12-22
申请人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
发明人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
IPC分类号： H01L27/108
CPC分类号： H01L29/517 , H01L21/28194 , H01L21/28202 , H01L29/1054 , H01L29/513 , H01L29/518 , H01L29/78
摘要： A semiconductor device and process including a high-k gate dielectric is described. A substrate is provided, and a high-k gate dielectric material, preferably amorphous HfSiON, is deposited over the substrate. In preferred embodiments, the high-k dielectric material includes nitrogen. In a preferred embodiment, a silicon nitride layer is deposited using jet vapor deposition (JVD) on the high-k dielectric material. When the JVD nitride layer is deposited according to preferred embodiments, the layer has a low density of charge traps, it maintains comparable carrier mobility and provides better EOT compared to oxide or oxynitride. A second nitrogen-containing layer formed between the high-k dielectric and the gate electrode acts as a diffusion barrier. It also reduces problems relating to oxygen vacancy formation in high-k dielectric and therefore minimizes Fermi-level pinning.
摘要翻译：描述了包括高k栅极电介质的半导体器件和工艺。提供衬底，并且在衬底上沉积高k栅介质材料，优选无定形HfSiON。在优选实施例中，高k电介质材料包括氮。在优选实施例中，使用喷射气相沉积（JVD）在高k电介质材料上沉积氮化硅层。当根据优选实施方案沉积JVD氮化物层时，该层具有低密度的电荷陷阱，与氧化物或氧氮化物相比，其维持可比较的载流子迁移率并提供更好的EOT。形成在高k电介质和栅电极之间的第二含氮层用作扩散阻挡层。它还减少了在高k电介质中与氧空位形成有关的问题，从而使费米能级钉扎最小化。

6. 发明申请

US20070187725A1 Method and apparatus for a semiconductor device with a high-k gate dielectric 有权
标题翻译：具有高k栅极电介质的半导体器件的方法和装置
公开(公告)号：US20070187725A1
公开(公告)日：2007-08-16
申请号：US11788229
申请日：2007-04-19
申请人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
发明人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
IPC分类号： H01L29/768 , H01L27/148
CPC分类号： H01L27/10894 , H01L21/28123 , H01L21/28194 , H01L21/823462 , H01L21/823468 , H01L21/823481 , H01L21/823857 , H01L21/823864 , H01L21/823878 , H01L27/10873 , H01L29/517
摘要： A process and apparatus for a high-k gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extend beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.
摘要翻译：描述了用于高k栅介质MOS晶体管的工艺和装置。提供衬底，在衬底上沉积高k栅极电介质材料，在电介质材料上沉积栅极电极层，并且执行构图步骤，其产生电极和电介质的侧壁并去除衬底的一部分。侧壁材料沉积在图案化的栅电极和电介质上，在图案化的栅电极和电介质上形成保护侧壁，该侧壁延伸在电介质的底部下方。在替代实施例中，沟道材料沉积在高k栅极电介质的下方，并且图案化步骤去除高k栅极电介质下方的沟道材料的至少一部分。在替代实施例中，沟道材料是反掺杂的。

7. 发明申请

US20060163672A1 High performance CMOS device design 有权
公开(公告)号：US20060163672A1
公开(公告)日：2006-07-27
申请号：US11115484
申请日：2005-04-27
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.

8. 发明授权

US08507951B2 High performance CMOS device design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US08507951B2
公开(公告)日：2013-08-13
申请号：US12330961
申请日：2008-12-09
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L29/66
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant than the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

9. 发明授权

US07564108B2 Nitrogen treatment to improve high-k gate dielectrics 有权
标题翻译：氮处理改善高k栅极电介质
公开(公告)号：US07564108B2
公开(公告)日：2009-07-21
申请号：US11115932
申请日：2005-04-27
申请人： Chih-Hao Wang , Ta-Wei Wang , Shang-Chih Chen , Ching-Wei Tsai
发明人： Chih-Hao Wang , Ta-Wei Wang , Shang-Chih Chen , Ching-Wei Tsai
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462 , H01L21/28202 , H01L21/76829 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A MOSFET having a nitrided gate dielectric and its manufacture are disclosed. The method comprises providing a substrate and depositing a non-high-k dielectric material on the substrate. The non-high-k dielectric comprises two layers. The first layer adjacent the substrate is essentially nitrogen-free, and the second layer includes between about 1015 atoms/cm3 to about 1022 atoms/cm3 nitrogen. The MOSFET further includes a high-k dielectric material on the nitrided, non-high-k dielectric. The high-k dielectric preferably includes HfSiON, ZrSiON, or nitrided Al2O3. Embodiments further include asymmetric manufacturing techniques wherein core and peripheral integrated circuit areas are separately optimized.
摘要翻译：公开了具有氮化栅极电介质的MOSFET及其制造。该方法包括提供衬底并在衬底上沉积非高k电介质材料。非高k电介质包括两层。与衬底相邻的第一层基本上是无氮的，第二层包括约1015个原子/ cm3到约1022个原子/ cm3的氮。 MOSFET还包括在氮化的非高k电介质上的高k电介质材料。高k电介质优选包括HfSiON，ZrSiON或氮化Al 2 O 3。实施例还包括其中核心和外围集成电路区域被分开优化的不对称制造技术。

10. 发明授权

US07332407B2 Method and apparatus for a semiconductor device with a high-k gate dielectric 有权
标题翻译：具有高k栅极电介质的半导体器件的方法和装置
公开(公告)号：US07332407B2
公开(公告)日：2008-02-19
申请号：US11788229
申请日：2007-04-19
申请人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
发明人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
IPC分类号： H01L21/76
CPC分类号： H01L27/10894 , H01L21/28123 , H01L21/28194 , H01L21/823462 , H01L21/823468 , H01L21/823481 , H01L21/823857 , H01L21/823864 , H01L21/823878 , H01L27/10873 , H01L29/517
摘要： A process and apparatus for a high-k gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extend beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.
摘要翻译：描述了用于高k栅介质MOS晶体管的工艺和装置。提供衬底，在衬底上沉积高k栅极电介质材料，在电介质材料上沉积栅极电极层，并且执行构图步骤，其产生电极和电介质的侧壁并去除衬底的一部分。侧壁材料沉积在图案化的栅电极和电介质上，在图案化的栅电极和电介质上形成保护侧壁，该侧壁延伸在电介质的底部下方。在替代实施例中，沟道材料沉积在高k栅极电介质的下方，并且图案化步骤去除高k栅极电介质下方的沟道材料的至少一部分。在替代实施例中，沟道材料是反掺杂的。

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