会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • High performance CMOS device design
    • 高性能CMOS器件设计
    • US07465972B2
    • 2008-12-16
    • US11115484
    • 2005-04-27
    • Chih-Hao WangShang-Chih ChenChing-Wei TsaiTa-Wei WangPang-Yen Tsai
    • Chih-Hao WangShang-Chih ChenChing-Wei TsaiTa-Wei WangPang-Yen Tsai
    • H01L31/62
    • H01L21/823807H01L21/823814H01L29/1054H01L29/66553H01L29/66636
    • A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.
    • 半导体器件包括栅极,栅极包括位于栅极电极下方的栅极电极和栅极电介质,形成在栅极电极和栅极电介质的侧壁上的间隔物,缓冲层,其具有位于栅极电介质下方的第一部分和间隔物 以及与间隔物相邻的第二部分,其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷,并且基本上与间隔物对准的源极/漏极区域。 缓冲层优选具有比下面的半导体衬底更大的晶格常数。 半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层,其中半导体覆盖层具有比缓冲层更小的晶格常数。
    • 5. 发明授权
    • Semiconductor device and method for high-k gate dielectrics
    • 用于高k栅极电介质的半导体器件和方法
    • US07355235B2
    • 2008-04-08
    • US11020377
    • 2004-12-22
    • Chih-Hao WangChing-Wei TsaiShang-Chih Chen
    • Chih-Hao WangChing-Wei TsaiShang-Chih Chen
    • H01L27/108
    • H01L29/517H01L21/28194H01L21/28202H01L29/1054H01L29/513H01L29/518H01L29/78
    • A semiconductor device and process including a high-k gate dielectric is described. A substrate is provided, and a high-k gate dielectric material, preferably amorphous HfSiON, is deposited over the substrate. In preferred embodiments, the high-k dielectric material includes nitrogen. In a preferred embodiment, a silicon nitride layer is deposited using jet vapor deposition (JVD) on the high-k dielectric material. When the JVD nitride layer is deposited according to preferred embodiments, the layer has a low density of charge traps, it maintains comparable carrier mobility and provides better EOT compared to oxide or oxynitride. A second nitrogen-containing layer formed between the high-k dielectric and the gate electrode acts as a diffusion barrier. It also reduces problems relating to oxygen vacancy formation in high-k dielectric and therefore minimizes Fermi-level pinning.
    • 描述了包括高k栅极电介质的半导体器件和工艺。 提供衬底,并且在衬底上沉积高k栅介质材料,优选无定形HfSiON。 在优选实施例中,高k电介质材料包括氮。 在优选实施例中,使用喷射气相沉积(JVD)在高k电介质材料上沉积氮化硅层。 当根据优选实施方案沉积JVD氮化物层时,该层具有低密度的电荷陷阱,与氧化物或氧氮化物相比,其维持可比较的载流子迁移率并提供更好的EOT。 形成在高k电介质和栅电极之间的第二含氮层用作扩散阻挡层。 它还减少了在高k电介质中与氧空位形成有关的问题,从而使费米能级钉扎最小化。
    • 8. 发明授权
    • High performance CMOS device design
    • 高性能CMOS器件设计
    • US08507951B2
    • 2013-08-13
    • US12330961
    • 2008-12-09
    • Chih-Hao WangShang-Chih ChenChing-Wei TsaiTa-Wei WangPang-Yen Tsai
    • Chih-Hao WangShang-Chih ChenChing-Wei TsaiTa-Wei WangPang-Yen Tsai
    • H01L29/66
    • H01L21/823807H01L21/823814H01L29/1054H01L29/66553H01L29/66636
    • A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant than the buffer layer.
    • 半导体器件包括栅极,栅极包括位于栅极电极下方的栅极电极和栅极电介质,形成在栅极电极和栅极电介质的侧壁上的间隔物,缓冲层,其具有位于栅极电介质下方的第一部分和间隔物 以及与间隔物相邻的第二部分,其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷,并且基本上与间隔物对准的源极/漏极区域。 缓冲层优选具有比下面的半导体衬底更大的晶格常数。 半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层,其中半导体覆盖层具有比缓冲层更小的晶格常数。