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1. 发明申请

US20120319278A1 GAP FILLING METHOD FOR DUAL DAMASCENE PROCESS 有权
标题翻译： GAP填充方法双重DAMASCENE过程
公开(公告)号：US20120319278A1
公开(公告)日：2012-12-20
申请号：US13161701
申请日：2011-06-16
申请人： Chun-Chieh Lin , Hung-Wen Su , Minghsing Tsai , Syun-Ming Jang
发明人： Chun-Chieh Lin , Hung-Wen Su , Minghsing Tsai , Syun-Ming Jang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76877 , H01L21/76807 , H01L21/7681 , H01L21/76831 , H01L21/76834 , H01L21/76846 , H01L21/76885 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L29/511 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括形成具有多个第一开口的图案化电介质层。该方法包括在图案化的介电层上形成导电衬垫层，导电衬垫层部分填充第一开口。该方法包括在第一开口之外的导电衬垫层的部分上形成沟槽掩模层，从而形成多个第二开口，其中一部分形成在第一开口上。该方法包括在第一开口中沉积导电材料以形成多个通孔，并且在第二开口中形成多个金属线。该方法包括去除沟槽掩模层。

2. 发明授权

US07705340B2 Inflected magnetoresistive structures and memory cells having inflected magnetoresistive structures 失效
标题翻译：具有变形磁阻结构的变形磁阻结构和存储单元
公开(公告)号：US07705340B2
公开(公告)日：2010-04-27
申请号：US11163118
申请日：2005-10-05
申请人： Chun-Chieh Lin
发明人： Chun-Chieh Lin
IPC分类号： H01L47/00
CPC分类号： H01L27/228 , H01L43/08
摘要： Disclosed herein is a magnetoresistive structure having a non-planar form. Embodiments of the present MR structure includes those having at least one inflection between a first portion of the MR structure that is somewhat vertical relative to a substrate and a second portion of the MR structure that is somewhat horizontal relative to the substrate. Such a structure can be used for memory device, for example an MRAM memory device, wherein the memory density is increased compared to devices having prior planar MR structures without reducing the surface area of the MR structures.
摘要翻译：本文公开了具有非平面形式的磁阻结构。本发明的MR结构的实施例包括那些在MR结构的第一部分之间相对于衬底稍微垂直的第一部分和MR结构相对于衬底稍微水平的第二部分的至少一个拐点。这种结构可以用于存储器件，例如MRAM存储器件，其中与具有先前的平面MR结构的器件相比，存储器密度增加而不减小MR结构的表面积。

3. 发明授权

US07656433B2 Web camera 有权
标题翻译：网络摄像头
公开(公告)号：US07656433B2
公开(公告)日：2010-02-02
申请号：US11707967
申请日：2007-02-20
申请人： Chi-Hsien Wang , Wen-Ming Huang , Wei-Song Yeh , Chun-Chieh Lin , Kuan-Chou Chen
发明人： Chi-Hsien Wang , Wen-Ming Huang , Wei-Song Yeh , Chun-Chieh Lin , Kuan-Chou Chen
IPC分类号： H04N5/228 , H04N5/225 , H04N7/26
CPC分类号： H04N19/184 , H04N19/91
摘要： A web camera includes an image sensor, which takes an external image; a sensor interface, which is connected to the mage sensor to receive and convert the image taken by the image sensor into digital image data; at least one compression module, which is connected to the sensor interface to receive and compress the digital image data into compressed image data; and a USB interface, which is connected to the compression module to output the compressed image data to a host device having a USB interface port, such as a computer and a USB OTG device, for storage, playing back and other applications.
摘要翻译：网络摄像机包括拍摄外部图像的图像传感器; 传感器接口，其连接到法师传感器，以将图像传感器拍摄的图像接收并转换为数字图像数据; 至少一个压缩模块，其连接到传感器接口以将数字图像数据接收并压缩成压缩图像数据; 以及USB接口，其连接到压缩模块以将压缩的图像数据输出到具有诸如计算机和USB OTG设备的USB接口端口的主机设备，用于存储，回放和其他应用。

4. 发明授权

US07592619B2 Epitaxy layer and method of forming the same 有权
标题翻译：外延层及其形成方法
公开(公告)号：US07592619B2
公开(公告)日：2009-09-22
申请号：US11622490
申请日：2007-01-12
申请人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
发明人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
IPC分类号： H01L29/15
CPC分类号： C30B25/00 , C30B29/06 , C30B29/52 , Y10S438/933
摘要： A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.
摘要翻译：提供了形成均匀厚度的外延层的方法以改善表面平坦度。首先提供衬底，然后通过外延在衬底上形成Si基层。通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

5. 发明申请

US20090000908A1 Systems and methods for buffering articles in transport 审中-公开
标题翻译：运输中缓冲物品的系统和方法
公开(公告)号：US20090000908A1
公开(公告)日：2009-01-01
申请号：US12218625
申请日：2008-07-15
申请人： Michael D. Brain , Chun-Chieh Lin
发明人： Michael D. Brain , Chun-Chieh Lin
IPC分类号： B65G49/07 , G06F7/00
CPC分类号： B65G37/005 , B65G37/02 , B65G2201/0297 , H01L21/67276 , H01L21/67715 , H01L21/67769
摘要： A system for buffering articles in transport is provided. The system comprises a buffer module configured to buffer articles and a computing system. The buffer module includes a first conveyor configured to transport the articles and a transference node configured to transfer the articles between the first conveyor and an external location. The computing system is configured to maintain an inventory list including a present location of each of the articles buffered by the buffer module. The computing system is further configured to control operation of the buffer module to transfer a selected article among the buffered articles to the external location.
摘要翻译：提供了一种用于在运输中缓冲物品的系统。该系统包括被配置为缓冲物品和计算系统的缓冲模块。缓冲器模块包括构造成输送物品的第一传送器和被配置成在第一传送器和外部位置之间传送物品的传送节点。计算系统被配置为维护包括由缓冲器模块缓冲的每个文章的当前位置的清单列表。计算系统还被配置为控制缓冲器模块的操作以将缓冲的物品中的所选物品传送到外部位置。

6. 发明申请

US20080265256A1 MOS devices with improved source/drain regions with SiGe 有权
标题翻译：具有SiGe源极/漏极区域改善的MOS器件
公开(公告)号：US20080265256A1
公开(公告)日：2008-10-30
申请号：US11796369
申请日：2007-04-27
申请人： Chun-Chieh Lin , Wei-Hua Hsu , Yu-En Percy Chang , Chung Li Chang , Chi-Feng Cheng , Win Hung , Kishimoto Ko
发明人： Chun-Chieh Lin , Wei-Hua Hsu , Yu-En Percy Chang , Chung Li Chang , Chi-Feng Cheng , Win Hung , Kishimoto Ko
IPC分类号： H01L29/94
CPC分类号： H01L29/665 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a SiGe region in the semiconductor substrate and adjacent the gate stack, wherein the SiGe region has a first atomic percentage of germanium to germanium and silicon; and a silicide region over the SiGe region. The silicide region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is substantially lower than the first atomic percentage.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; SiGe区域，其中SiGe区域具有锗到锗和硅的第一原子百分比; 以及SiGe区域上的硅化物区域。硅化物区域具有锗与锗和硅的第二原子百分比。第二原子百分比基本上低于第一原子百分数。

7. 发明授权

US07423347B2 In-situ deposition for cu hillock suppression 有权
标题翻译：原位沉积用于小丘抑制
公开(公告)号：US07423347B2
公开(公告)日：2008-09-09
申请号：US11334849
申请日：2006-01-19
申请人： Chung-Hsien Chen , Chun-Chieh Lin , Minghsing Tsai , Shau-Lin Shue
发明人： Chung-Hsien Chen , Chun-Chieh Lin , Minghsing Tsai , Shau-Lin Shue
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53238 , H01L21/2885 , H01L21/76877 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.
摘要翻译：提供了具有减小的小丘形成的半导体互连结构及其形成方法。半导体互连结构包括形成在电介质层中的导体。导体包括至少三个子层，其中相邻子层中杂质浓度的比优选大于约2。

8. 发明授权

US07381604B2 Strained-channel semiconductor structure and method for fabricating the same 有权
标题翻译：应变通道半导体结构及其制造方法
公开(公告)号：US07381604B2
公开(公告)日：2008-06-03
申请号：US11423457
申请日：2006-06-12
申请人： Chun-Chieh Lin , Yee-Chia Yeo
发明人： Chun-Chieh Lin , Yee-Chia Yeo
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/76224 , H01L21/823412 , H01L29/165 , H01L29/6659 , H01L29/66628 , H01L29/7848
摘要： A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region. A pair of source/drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source/drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.
摘要翻译：应变通道半导体结构及其制造方法。应变通道半导体结构包括由具有第一自然晶格常数的第一半导体材料构成的衬底。通道区域设置在衬底中，并且栅堆叠设置在应变通道区域上。一对源极/漏极区域相邻地设置在衬底中，与沟道区域相邻，其中源极/漏极区域中的每个源极/漏极区域包括具有第二自然晶格常数而不是第一自然晶格的第二半导体材料的晶格失配区域常数，对应于栅极叠层的内侧和外侧，并且至少一个外侧横向接触基板的第一半导体材料。

9. 发明授权

US07357838B2 Relaxed silicon germanium substrate with low defect density 有权
标题翻译：具有低缺陷密度的松弛硅锗衬底
公开(公告)号：US07357838B2
公开(公告)日：2008-04-15
申请号：US11074738
申请日：2005-03-08
申请人： Chun Chieh Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
发明人： Chun Chieh Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
IPC分类号： C30B23/00
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/324
摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe is provided.
摘要翻译：提供了在松弛的低缺陷密度半导体合金层（例如SiGe）上形成应变硅层的方法。

10. 发明申请

US20070164439A1 In-situ deposition for cu hillock suppression 有权
标题翻译：原位沉积用于小丘抑制
公开(公告)号：US20070164439A1
公开(公告)日：2007-07-19
申请号：US11334849
申请日：2006-01-19
申请人： Chung-Hsien Chen , Chun-Chieh Lin , Minghsing Tsai , Shau-Lin Shue
发明人： Chung-Hsien Chen , Chun-Chieh Lin , Minghsing Tsai , Shau-Lin Shue
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/2885 , H01L21/76877 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.
摘要翻译：提供了具有减小的小丘形成的半导体互连结构及其形成方法。半导体互连结构包括形成在电介质层中的导体。导体包括至少三个子层，其中相邻子层中杂质浓度的比优选大于约2。

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