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1. 发明申请

US20060163672A1 High performance CMOS device design 有权
公开(公告)号：US20060163672A1
公开(公告)日：2006-07-27
申请号：US11115484
申请日：2005-04-27
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.

2. 发明申请

US20090090935A1 High Performance CMOS Device Design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US20090090935A1
公开(公告)日：2009-04-09
申请号：US12330961
申请日：2008-12-09
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L29/78
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

3. 发明授权

US07465972B2 High performance CMOS device design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US07465972B2
公开(公告)日：2008-12-16
申请号：US11115484
申请日：2005-04-27
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L31/62
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

4. 发明授权

US08507951B2 High performance CMOS device design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US08507951B2
公开(公告)日：2013-08-13
申请号：US12330961
申请日：2008-12-09
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L29/66
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant than the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

5. 发明授权

US07615426B2 PMOS transistor with discontinuous CESL and method of fabrication 有权
标题翻译：具有不连续CESL的PMOS晶体管及其制造方法
公开(公告)号：US07615426B2
公开(公告)日：2009-11-10
申请号：US11118730
申请日：2005-04-29
申请人： Chih-Hao Wang , Yen-Ping Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Yen-Ping Wang , Pang-Yen Tsai
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/76 , H01L29/94 , H01L27/01
CPC分类号： H01L29/165 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7848 , H01L29/7849
摘要： A transistor having a discontinuous contact etch stop layer comprising: a substrate having a surface, a gate dielectric on said surface of said substrate, a gate electrode on said gate dielectric, a spacer along a sidewall of said gate dielectric and gate electrode, a source and a drain formed on opposite sides, respectively, of said gate dielectric and said gate electrode, the source and drain defining a channel region having a channel length extending substantially from said source to said drain, in the substrate therebetween, and a contact etch stop layer on said gate and said spacers, and said source and drain. The contact etch stop layer is substantially locally continuous in a direction perpendicular to the channel region length and substantially locally discontinuous in a direction parallel to the channel region length.
摘要翻译：一种具有不连续接触蚀刻停止层的晶体管，包括：具有表面的衬底，所述衬底的所述表面上的栅极电介质，所述栅极电介质上的栅极电极，沿着所述栅极电介质和栅电极的侧壁的间隔物，源极以及分别在所述栅极电介质和所述栅电极的相对侧上形成的漏极，所述源极和漏极限定了沟道区，所述沟道区具有基本上从所述源延伸到所述漏极的沟道长度，以及在其间的衬底中的接触蚀刻停止所述栅极和所述间隔物上的层，以及所述源极和漏极。接触蚀刻停止层在垂直于沟道区长度的方向上基本上局部连续，并且在平行于沟道区长度的方向上基本上局部不连续。

6. 发明申请

US20060189053A1 PMOS transistor with discontinuous CESL and method of fabrication 有权
公开(公告)号：US20060189053A1
公开(公告)日：2006-08-24
申请号：US11118730
申请日：2005-04-29
申请人： Chih-Hao Wang , Yen-Ping Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Yen-Ping Wang , Pang-Yen Tsai
IPC分类号： H01L21/8234
CPC分类号： H01L29/165 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7843 , H01L29/7848 , H01L29/7849
摘要： A transistor having a discontinuous contact etch stop layer comprising: a substrate having a surface, a gate dielectric on said surface of said substrate, a gate electrode on said gate dielectric, a spacer along a sidewall of said gate dielectric and gate electrode, a source and a drain formed on opposite sides, respectively, of said gate dielectric and said gate electrode, the source and drain defining a channel region having a channel length extending substantially from said source to said drain, in the substrate therebetween, and a contact etch stop layer on said gate and said spacers, and said source and drain. The contact etch stop layer is substantially locally continuous in a direction perpendicular to the channel region length and substantially locally discontinuous in a direction parallel to the channel region length.

7. 发明授权

US07592619B2 Epitaxy layer and method of forming the same 有权
标题翻译：外延层及其形成方法
公开(公告)号：US07592619B2
公开(公告)日：2009-09-22
申请号：US11622490
申请日：2007-01-12
申请人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
发明人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
IPC分类号： H01L29/15
CPC分类号： C30B25/00 , C30B29/06 , C30B29/52 , Y10S438/933
摘要： A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.
摘要翻译：提供了形成均匀厚度的外延层的方法以改善表面平坦度。首先提供衬底，然后通过外延在衬底上形成Si基层。通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

8. 发明申请

US20080132019A1 Short channel effect engineering in MOS device using epitaxially carbon-doped silicon 有权
标题翻译：使用外延碳掺杂硅的MOS器件中的短沟道效应工程
公开(公告)号：US20080132019A1
公开(公告)日：2008-06-05
申请号：US11633721
申请日：2006-12-05
申请人： Keh-Chiang Ku , Pang-Yen Tsai , Chun-Feng Nieh , Li-Ting Wang
发明人： Keh-Chiang Ku , Pang-Yen Tsai , Chun-Feng Nieh , Li-Ting Wang
IPC分类号： H01L21/04
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/1083 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, and epitaxially growing a lightly-doped source/drain (LDD) region adjacent the gate stack, wherein carbon is simultaneously doped into the LDD region.
摘要翻译：一种用于形成半导体结构的方法包括提供半导体衬底，在半导体衬底上形成栅极堆叠，以及外围生长与栅堆叠相邻的轻掺杂源极/漏极（LDD）区域，其中碳同时掺杂到LDD区域。

9. 发明申请

US20070148919A1 Multi-step epitaxial process for depositing Si/SiGe 有权
标题翻译：用于沉积Si / SiGe的多步外延工艺
公开(公告)号：US20070148919A1
公开(公告)日：2007-06-28
申请号：US11313768
申请日：2005-12-22
申请人： Li-Te Lin , Pang-Yen Tsai , Chih-Chien Chang , Tze-Liang Lee
发明人： Li-Te Lin , Pang-Yen Tsai , Chih-Chien Chang , Tze-Liang Lee
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/0262 , H01L21/02661
摘要： A method for manufacturing a semiconductor device includes providing a substrate comprising silicon, cleaning the substrate, performing a first low pressure chemical vapor deposition (LPCVD) process using a first source gas to selectively deposit a seeding layer of silicon (Si) over the substrate, performing a second LPCVD process using a second source gas to selectively deposit a first layer of silicon germanium (SiGe) over the layer of Si, the second source gas including hydrochloride at a first flow rate, and performing a third LPCVD process using a third source gas including hydrochloride at a second flow rate. The first flow rate is substantially lower than the second flow rate.
摘要翻译：一种制造半导体器件的方法包括提供包括硅的衬底，清洁衬底，使用第一源气体执行第一低压化学气相沉积（LPCVD）工艺，以在衬底上选择性地沉积硅（Si）晶种层，使用第二源气体执行第二LPCVD处理，以选择性地在所述Si层上沉积第一层硅锗（SiGe），所述第二源气体以第一流速包括盐酸盐，并且使用第三源进行第三LPCVD处理气体包括盐酸盐以第二流量。第一流速基本上低于第二流量。

10. 发明授权

US07175709B2 Epitaxy layer and method of forming the same 有权
标题翻译：外延层及其形成方法
公开(公告)号：US07175709B2
公开(公告)日：2007-02-13
申请号：US10847099
申请日：2004-05-17
申请人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
发明人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
IPC分类号： C30B25/04
CPC分类号： C30B25/00 , C30B29/06 , C30B29/52 , Y10S438/933
摘要： A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.
摘要翻译：提供了形成均匀厚度的外延层的方法以改善表面平坦度。首先提供衬底，然后通过外延在衬底上形成Si基层。通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

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