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1. 发明申请

US20120083076A1 Ultra-Shallow Junction MOSFET Having a High-k Gate Dielectric and In-Situ Doped Selective Epitaxy Source/Drain Extensions and a Method of Making Same 有权
标题翻译：具有高k栅介质和原位掺杂选择性外延源/漏极扩展的超浅结结MOSFET及其制作方法
公开(公告)号：US20120083076A1
公开(公告)日：2012-04-05
申请号：US13324592
申请日：2011-12-13
申请人： Chih-Hao Wang , Shang-Chih Chen , Yen-Ping Wang , Hsien-Kuang Chiu , Liang-Gi Yao , Chenming Hu
发明人： Chih-Hao Wang , Shang-Chih Chen , Yen-Ping Wang , Hsien-Kuang Chiu , Liang-Gi Yao , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7833
摘要： A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.
摘要翻译： MOSFET包括在衬底上具有高k栅极电介质的栅极和栅极电介质上的栅极电极。栅极电介质突出超过栅电极。在栅极的任一侧形成具有浅延伸的深源极和漏极。深源和漏极通过选择性原位掺杂外延或通过离子注入形成，并且通过选择性原位掺杂外延形成延伸。延伸部位于与栅极电介质接触的栅极下方。选择栅极电介质的材料和其突出超过栅电极的量，使得外延程序和相关过程不会引起栅极电极和源极/漏极延伸部之间的桥接。描述制造MOSFET的方法。

2. 发明授权

US08759185B2 Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same 有权
标题翻译：具有高k栅极电介质和原位掺杂的选择性外延源极/漏极延伸的超浅结结MOSFET及其制造方法
公开(公告)号：US08759185B2
公开(公告)日：2014-06-24
申请号：US13324592
申请日：2011-12-13
申请人： Chih-Hao Wang , Shang-Chih Chen , Yen-Ping Wang , Hsien-Kuang Chiu , Liang-Gi Yao , Chenming Hu
发明人： Chih-Hao Wang , Shang-Chih Chen , Yen-Ping Wang , Hsien-Kuang Chiu , Liang-Gi Yao , Chenming Hu
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7833
摘要： A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.
摘要翻译： MOSFET包括在衬底上具有高k栅极电介质的栅极和栅极电介质上的栅极电极。栅极电介质突出超过栅电极。在栅极的任一侧形成具有浅延伸的深源极和漏极。深源和漏极通过选择性原位掺杂外延或通过离子注入形成，并且通过选择性原位掺杂外延形成延伸。延伸部位于与栅极电介质接触的栅极下方。选择栅极电介质的材料和其突出超过栅电极的量，使得外延程序和相关过程不会引起栅极电极和源极/漏极延伸部之间的桥接。描述制造MOSFET的方法。

3. 发明授权

US08097924B2 Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same 有权
标题翻译：具有高k栅极电介质和原位掺杂的选择性外延源极/漏极延伸的超浅结结MOSFET及其制造方法
公开(公告)号：US08097924B2
公开(公告)日：2012-01-17
申请号：US10872095
申请日：2004-06-18
申请人： Chih-Hao Wang , Shang-Chih Chen , Yen-Ping Wang , Hsien-Kuang Chiu , Liang-Gi Yao , Chenming Hu
发明人： Chih-Hao Wang , Shang-Chih Chen , Yen-Ping Wang , Hsien-Kuang Chiu , Liang-Gi Yao , Chenming Hu
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/1054 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7833
摘要： A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.
摘要翻译： MOSFET包括在衬底上具有高k栅极电介质的栅极和栅极电介质上的栅极电极。栅极电介质突出超过栅电极。在栅极的任一侧形成具有浅延伸的深源极和漏极。深源和漏极通过选择性原位掺杂外延或通过离子注入形成，并且通过选择性原位掺杂外延形成延伸。延伸部位于与栅极电介质接触的栅极下方。选择栅极电介质的材料和其突出超过栅电极的量，使得外延程序和相关过程不会引起栅极电极和源极/漏极延伸部之间的桥接。描述制造MOSFET的方法。

4. 发明申请

US20050093084A1 Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same 有权
标题翻译：具有高k栅极电介质和原位掺杂的选择性外延源极/漏极延伸的超浅结结MOSFET及其制造方法
公开(公告)号：US20050093084A1
公开(公告)日：2005-05-05
申请号：US10872095
申请日：2004-06-18
申请人： Chih-Hao Wang , Shang-Chih Chen , Yen-Ping Wang , Hsien-Kuang Chiu , Liang-Gi Yao , Chenming Hu
发明人： Chih-Hao Wang , Shang-Chih Chen , Yen-Ping Wang , Hsien-Kuang Chiu , Liang-Gi Yao , Chenming Hu
IPC分类号： H01L21/28 , H01L21/336 , H01L29/10 , H01L29/51 , H01L29/78 , H01L29/76
CPC分类号： H01L29/1054 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7833
摘要： A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.
摘要翻译： MOSFET包括在衬底上具有高k栅极电介质的栅极和栅极电介质上的栅极电极。栅极电介质突出超过栅电极。在栅极的任一侧形成具有浅延伸的深源极和漏极。深源和漏极通过选择性原位掺杂外延或通过离子注入形成，并且通过选择性原位掺杂外延形成延伸。延伸部位于与栅极电介质接触的栅极下方。选择栅极电介质的材料和其突出超过栅电极的量，使得外延程序和相关过程不会引起栅极电极和源极/漏极延伸部之间的桥接。描述制造MOSFET的方法。

5. 发明授权

US06777299B1 Method for removal of a spacer 失效
标题翻译：去除垫片的方法
公开(公告)号：US06777299B1
公开(公告)日：2004-08-17
申请号：US10614388
申请日：2003-07-07
申请人： Hsien-Kuang Chiu , Chih-Hao Wang
发明人： Hsien-Kuang Chiu , Chih-Hao Wang
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/31111 , H01L21/31138 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a method and system for removing a spacer, such as associated with a processing operation using a lightly doped drain (LDD) region. The method includes defining an electrode on a substrate, forming a spacer adjacent to at least one sidewall of the electrode, and performing a processing operation on the substrate. The processing operation, which can be an ion implantation process, can use the spacer as a mask, and as a result can create a layer, such as a polymer, on the spacer. The spacer can then be removed by applying a first dry etch process to remove the layer on the spacer and a second wet etch process to remove the spacer. The first dry etch utilizes a fluorine-contained plasma, such as one that uses a CF4, CHF3, CH2F2, or CH3F etchant. A third wet etch process can be used to remove an oxide layer underlying the spacer.
摘要翻译：本公开提供了用于去除间隔物的方法和系统，例如与使用轻掺杂漏极（LDD）区域的处理操作相关联。该方法包括在衬底上限定电极，形成与电极的至少一个侧壁相邻的间隔物，并在衬底上执行处理操作。可以使用离子注入工艺的处理操作可以使用间隔物作为掩模，结果可以在间隔物上形成诸如聚合物的层。然后可以通过施加第一干蚀刻工艺去除间隔物上的层并且进行第二湿蚀刻工艺以去除间隔物来移除间隔物。第一次干蚀刻使用含氟等离子体，例如使用CF 4，CHF 3，CH 2 F 2或CH 3 F蚀刻剂的等离子体。可以使用第三湿法蚀刻工艺去除衬垫下面的氧化物层。

6. 发明授权

US07235153B2 System for removal of a spacer 有权
标题翻译：用于移除垫片的系统
公开(公告)号：US07235153B2
公开(公告)日：2007-06-26
申请号：US10894199
申请日：2004-07-19
申请人： Hsien-Kuang Chiu , Chih-Hao Wang
发明人： Hsien-Kuang Chiu , Chih-Hao Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L21/31111 , H01L21/31138 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a system for removing a spacer, such as associated with a processing operation using a lightly doped drain (LDD) region. In one example, the system includes means for creating a spacer, means for implanting a first relatively heavily doped region with the spacer in place, one or more chambers for removing the spacer, and means for implanting the LDD region with the spacer removed. The one or more chambers may be configured for applying a first dry removal process to remove the layer on the spacer utilizing a fluorine-contained plasma and applying a second wet etch process to remove the spacer.
摘要翻译：本公开提供了一种用于去除间隔物的系统，例如与使用轻掺杂漏极（LDD）区域的处理操作相关联的系统。在一个示例中，该系统包括用于产生间隔物的装置，用于将间隔件第一相对重掺杂的区域注入适当位置的装置，用于移除间隔物的一个或多个室以及用于移除间隔物的LDD区域的注入装置。一个或多个室可以被配置为施加第一干燥去除工艺以利用含氟等离子体去除间隔物上的层，并施加第二湿法蚀刻工艺以去除间隔物。

7. 发明申请

US20050006708A1 Method for removal of a spacer 审中-公开
标题翻译：去除垫片的方法
公开(公告)号：US20050006708A1
公开(公告)日：2005-01-13
申请号：US10894172
申请日：2004-07-19
申请人： Hsien-Kuang Chiu , Chih-Hao Wang
发明人： Hsien-Kuang Chiu , Chih-Hao Wang
IPC分类号： H01L21/311 , H01L21/336 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/31111 , H01L21/31138 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a semiconductor device having a region, such as a lightly doped drain (LDD) region, formed using a disposable spacer. In one example, the device includes a substrate, an electrode formed on the substrate, and first and second regions in the substrate. The first region is relatively deep and spaced a first distance from the electrode. The second region is relatively shallow and spaced a second distance from the electrode, with the second distance being less than the first distance. The second region is produced through use of a disposable spacer positioned adjacent to a side wall of the electrode, where the substrate remains undamaged by a phosphoric acid process used to remove the spacer.
摘要翻译：本公开提供了一种半导体器件，其具有使用一次性间隔物形成的区域，例如轻掺杂漏极（LDD）区域。在一个示例中，该器件包括衬底，形成在衬底上的电极以及衬底中的第一和第二区域。第一区域相对较深并与电极隔开第一距离。第二区域相对较浅并与电极隔开第二距离，第二距离小于第一距离。第二区域通过使用邻近电极的侧壁定位的一次性间隔件来生产，其中基底通过用于移除间隔物的磷酸工艺保持不损坏。

8. 发明申请

US20050009283A1 Method for removal of a spacer 有权
标题翻译：去除垫片的方法
公开(公告)号：US20050009283A1
公开(公告)日：2005-01-13
申请号：US10894199
申请日：2004-07-19
申请人： Hsien-Kuang Chiu , Chih-Hao Wang
发明人： Hsien-Kuang Chiu , Chih-Hao Wang
IPC分类号： H01L21/311 , H01L21/336 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/31111 , H01L21/31138 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a system for removing a spacer, such as associated with a processing operation using a lightly doped drain (LDD) region. In one example, the system includes means for creating a spacer, means for implanting a first relatively heavily doped region with the spacer in place, one or more chambers for removing the spacer, and means for implanting the LDD region with the spacer removed. The one or more chambers may be configured for applying a first dry removal process to remove the layer on the spacer utilizing a fluorine-contained plasma and applying a second wet etch process to remove the spacer.
摘要翻译：本公开提供了一种用于去除间隔物的系统，例如与使用轻掺杂漏极（LDD）区域的处理操作相关联的系统。在一个示例中，该系统包括用于产生间隔物的装置，用于将间隔件第一相对重掺杂的区域注入适当位置的装置，用于移除间隔物的一个或多个室以及用于移除间隔物的LDD区域的注入装置。一个或多个室可以被配置为施加第一干燥去除工艺以利用含氟等离子体去除间隔物上的层，并施加第二湿法蚀刻工艺以去除间隔物。

9. 发明申请

US20050181590A1 Process for patterning high-k dielectric material 有权
标题翻译：图案化高k电介质材料的工艺
公开(公告)号：US20050181590A1
公开(公告)日：2005-08-18
申请号：US11101774
申请日：2005-04-08
申请人： Hsien-Kuang Chiu , Baw-Ching Perng , Hun-Jan Tao
发明人： Hsien-Kuang Chiu , Baw-Ching Perng , Hun-Jan Tao
IPC分类号： C23F1/00 , H01L21/20 , H01L21/28 , H01L21/306 , H01L21/311 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L29/78
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method further includes a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.
摘要翻译：提供了一种图案化高k介电材料层的方法，其可用于制造半导体器件。在高k电介质层上进行第一蚀刻。在第一蚀刻之后，用第一蚀刻蚀刻的高k电介质层的一部分保留。执行高k电介质层的第二蚀刻以去除高k电介质层的剩余部分。第二蚀刻不同于第一蚀刻。优选地，第一蚀刻是干蚀刻工艺，第二蚀刻是湿蚀刻工艺。该方法还包括在第一次蚀刻之后和第二次蚀刻之前等离子体灰化高k电介质层的剩余部分的工艺。

10. 发明授权

US07037849B2 Process for patterning high-k dielectric material 失效
标题翻译：图案化高k电介质材料的工艺
公开(公告)号：US07037849B2
公开(公告)日：2006-05-02
申请号：US10608349
申请日：2003-06-27
申请人： Hsien-Kuang Chiu , Baw-Ching Perng , Hun-Jan Tao
发明人： Hsien-Kuang Chiu , Baw-Ching Perng , Hun-Jan Tao
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method may further include a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.
摘要翻译：提供了一种图案化高k介电材料层的方法，其可用于制造半导体器件。在高k电介质层上进行第一蚀刻。在第一次蚀刻之后，用第一蚀刻蚀刻的高k电介质层的一部分保留。执行高k电介质层的第二蚀刻以去除高k电介质层的剩余部分。第二蚀刻不同于第一蚀刻。优选地，第一蚀刻是干蚀刻工艺，第二蚀刻是湿蚀刻工艺。该方法还可以包括在第一次蚀刻之后和第二次蚀刻之前等离子体灰化高k电介质层的剩余部分的工艺。

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