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1. 发明授权

US07229893B2 Method and apparatus for a semiconductor device with a high-k gate dielectric 有权
标题翻译：具有高k栅极电介质的半导体器件的方法和装置
公开(公告)号：US07229893B2
公开(公告)日：2007-06-12
申请号：US11021269
申请日：2004-12-23
申请人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
发明人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L21/823468 , H01L21/823481 , H01L27/10852 , H01L27/10873 , H01L27/10894
摘要： A process and apparatus for a high gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extends beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.
摘要翻译：描述了一种高栅极介电MOS晶体管的工艺和装置。提供衬底，在衬底上沉积高k栅极电介质材料，在电介质材料上沉积栅极电极层，并且执行构图步骤，其产生电极和电介质的侧壁并去除衬底的一部分。侧壁材料沉积在图案化的栅极电极上，并且在图案化的栅电极和在电介质的底部下方延伸的电介质上形成电介质。在替代实施例中，沟道材料沉积在高k栅极电介质的下方，并且图案化步骤去除高k栅极电介质下方的沟道材料的至少一部分。在替代实施例中，沟道材料是反掺杂的。

2. 发明申请

US20070001217A1 Closed loop CESL high performance CMOS devices 有权
标题翻译：闭环CESL高性能CMOS器件
公开(公告)号：US20070001217A1
公开(公告)日：2007-01-04
申请号：US11170201
申请日：2005-06-29
申请人： Shang-Chih Chen , Shih-Hsieng Huang , Chih-Hao Wang
发明人： Shang-Chih Chen , Shih-Hsieng Huang , Chih-Hao Wang
IPC分类号： H01L29/788
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/6656 , H01L29/7833 , H01L29/7843 , Y10S257/90
摘要： An N-MOS and/or P-MOS device having enhanced performance such as an FET suitable for use in a CMOS circuit. The device comprises both an “L-like” shaped layer or spacer on the side walls of a gate structure as well as a CESL (contact-etch stop layer) that covers the gate structure and surrounding substrate to induce increase tensile stresses in the N-MOS device and increased compressive stresses in the P-MOS device.
摘要翻译：具有增强性能的N-MOS和/或P-MOS器件，例如适用于CMOS电路的FET。该器件包括栅极结构的侧壁上的“L形”形状的层或间隔物以及覆盖栅极结构和周围衬底的CESL（接触蚀刻停止层），以在N中引起增加的拉伸应力 -MOS器件和P-MOS器件中增加的压应力。

3. 发明申请

US20050287759A1 Method and apparatus for a semiconductor device with a high-k gate dielectric 有权
标题翻译：具有高k栅极电介质的半导体器件的方法和装置
公开(公告)号：US20050287759A1
公开(公告)日：2005-12-29
申请号：US11021269
申请日：2004-12-23
申请人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
发明人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
IPC分类号： H01L21/00 , H01L21/8234 , H01L21/8242
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L21/823468 , H01L21/823481 , H01L27/10852 , H01L27/10873 , H01L27/10894
摘要： A process and apparatus for a high gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is performed creating sidewalls of the electrode and dielectric and removing a portion of the substrate. Sidewall material is deposited over the patterned gate electrode and dielectric creating protective sidewalls on the patterned gate electrode and dielectric that extends beneath the bottom of the dielectric. In alternative embodiments a channel material is deposited beneath the high-k gate dielectric and the patterning step removes at least a portion of the channel material beneath the high-k gate dielectric. In alternative embodiments the channel material is counter-doped.
摘要翻译：描述了一种高栅极介电MOS晶体管的工艺和装置。提供衬底，在衬底上沉积高k栅极电介质材料，在电介质材料上沉积栅极电极层，并且执行构图步骤，其产生电极和电介质的侧壁并去除衬底的一部分。侧壁材料沉积在图案化的栅极电极上，并且在图案化的栅电极和在电介质的底部下方延伸的电介质上形成电介质。在替代实施例中，沟道材料沉积在高k栅极电介质的下方，并且图案化步骤去除高k栅极电介质下方的沟道材料的至少一部分。在替代实施例中，沟道材料是反掺杂的。

4. 发明申请

US20050035345A1 Semiconductor device with high-k gate dielectric 有权
标题翻译：具有高k栅极电介质的半导体器件
公开(公告)号：US20050035345A1
公开(公告)日：2005-02-17
申请号：US10832020
申请日：2004-04-26
申请人： Chun-Chieh Lin , Wen-Chin Lee , Chenming Hu , Shang-Chih Chen , Chih-Hao Wang , Fu-Liang Yang , Yee-Chia Yeo
发明人： Chun-Chieh Lin , Wen-Chin Lee , Chenming Hu , Shang-Chih Chen , Chih-Hao Wang , Fu-Liang Yang , Yee-Chia Yeo
IPC分类号： H01L21/28 , H01L21/8234 , H01L29/51 , H01L29/06
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/823462 , H01L29/513 , H01L29/517 , H01L29/518
摘要： An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.
摘要翻译：集成电路包括衬底，第一晶体管和第二晶体管。第一晶体管具有位于第一栅电极和衬底之间的第一栅电介质部分。第一栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。第一栅介质部分具有第一等效氧化硅厚度。第二晶体管具有位于第二栅电极和衬底之间的第二栅介质部分。第二栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。第二栅介质部分具有第二等效氧化硅厚度。第二等效氧化硅厚度可以不同于第一等效氧化硅厚度。

5. 发明授权

US07829978B2 Closed loop CESL high performance CMOS device 有权
标题翻译：闭环CESL高性能CMOS器件
公开(公告)号：US07829978B2
公开(公告)日：2010-11-09
申请号：US11170201
申请日：2005-06-29
申请人： Shang-Chih Chen , Shih-Hsieng Huang , Chih-Hao Wang
发明人： Shang-Chih Chen , Shih-Hsieng Huang , Chih-Hao Wang
IPC分类号： H01L23/58
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/6656 , H01L29/7833 , H01L29/7843 , Y10S257/90
摘要： An N-MOS and/or P-MOS device having enhanced performance such as an FET suitable for use in a CMOS circuit. The device comprises both an “L-like” shaped layer or spacer on the side walls of a gate structure as well as a CESL (contact-etch stop layer) that covers the gate structure and surrounding substrate to induce increase tensile stresses in the N-MOS device and increased compressive stresses in the P-MOS device.
摘要翻译：具有增强性能的N-MOS和/或P-MOS器件，例如适用于CMOS电路的FET。该器件包括栅极结构的侧壁上的“L形”形状的层或间隔物以及覆盖栅极结构和周围衬底的CESL（接触蚀刻停止层），以在N中引起增加的拉伸应力 -MOS器件和P-MOS器件中增加的压应力。

6. 发明授权

US07763945B2 Strained spacer design for protecting high-K gate dielectric 有权
标题翻译：用于保护高K栅电介质的应变间隔设计
公开(公告)号：US07763945B2
公开(公告)日：2010-07-27
申请号：US11736755
申请日：2007-04-18
申请人： Chih-Hao Wang , Shang-Chih Chen
发明人： Chih-Hao Wang , Shang-Chih Chen
IPC分类号： H01L31/119
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/092 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A semiconductor device pair is provided. The semiconductor device pair comprises a semiconductor substrate comprising a first gate structure with a first type polarity and a second gate structure with a second type polarity, the first and the second gate structures comprise a high-K gate dielectric. A plurality of oxygen-free offset spacer portions are adjacent either side of the respective first and second gate structures, each comprising a stressed dielectric layer, to induce a desired strain on a respective channel region while sealing respective high-K gate dielectric sidewall portions, wherein the oxygen-free offset spacer portions adjacent either side of the first gate structure and the oxygen-free offset spacer portions adjacent either side of the second gate structure are formed with different shapes.
摘要翻译：提供半导体器件对。半导体器件对包括半导体衬底，其包括具有第一类型极性的第一栅极结构和具有第二类型极性的第二栅极结构，第一和第二栅极结构包括高K栅极电介质。多个无氧偏移间隔物部分相邻于相应的第一和第二栅极结构的每一侧，每一个包括应力介电层，以在相应的沟道区域上引起期望的应变，同时密封相应的高K栅介质侧壁部分，其中邻近所述第一栅极结构的任一侧的所述无氧偏移间隔物部分和邻近所述第二栅极结构的任一侧的所述无氧偏移间隔物部分形成为不同的形状。

7. 发明授权

US07465972B2 High performance CMOS device design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US07465972B2
公开(公告)日：2008-12-16
申请号：US11115484
申请日：2005-04-27
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L31/62
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

8. 发明申请

US20060177997A1 Methods of forming semiconductor devices with high-k gate dielectric 有权
标题翻译：用高k栅极电介质形成半导体器件的方法
公开(公告)号：US20060177997A1
公开(公告)日：2006-08-10
申请号：US11377105
申请日：2006-03-16
申请人： Chun-Chieh Lin , Wen-Chin Lee , Chenming Hu , Shang-Chih Chen , Chih-Hao Wang , Fu-Liang Yang , Yee-Chia Yeo
发明人： Chun-Chieh Lin , Wen-Chin Lee , Chenming Hu , Shang-Chih Chen , Chih-Hao Wang , Fu-Liang Yang , Yee-Chia Yeo
IPC分类号： H01L21/20
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/823462 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate dielectric portion is formed on the substrate in a second transistor region. The second gate dielectric portion includes the first high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness is different than the first equivalent silicon oxide thickness.
摘要翻译：提供一种制造集成电路的方法。第一栅介质部分形成在第一晶体管区域中的衬底上。第一栅介质部分包括第一高介电常数介电材料。第一栅介质部分具有第一等效氧化硅厚度。在第二晶体管区域中的衬底上形成第二栅介质部分。第二栅介质部分包括第一高电容率介电材料。第二栅介质部分具有第二等效氧化硅厚度。第二等效氧化硅厚度不同于第一等效氧化硅厚度。

9. 发明申请

US20060141729A1 System and method for suppressing oxide formation 有权
标题翻译：抑制氧化物形成的系统和方法
公开(公告)号：US20060141729A1
公开(公告)日：2006-06-29
申请号：US11025040
申请日：2004-12-29
申请人： Chih-Hao Wang , Shang-Chih Chen
发明人： Chih-Hao Wang , Shang-Chih Chen
IPC分类号： H01L21/331
CPC分类号： H01L21/0217 , H01L21/28176 , H01L21/28194 , H01L21/28247 , H01L21/3144 , H01L21/3185 , H01L29/4983 , H01L29/513 , H01L29/517 , H01L29/66636 , Y10S438/954
摘要： A system and method for suppressing sub-oxide formation during the manufacturing of semiconductor devices (such as MOSFET transistor) with high-k gate dielectric is disclosed. In one example, the MOSFET transistor includes a gate structure including a high-k gate dielectric and a gate electrode. In this example, the gate structure is covered with a nitride layer that is used to prevent oxygen from entering the structure during processing, yet is sufficiently thin to be effectively transparent to the processing.
摘要翻译：公开了一种用于在制造具有高k栅极电介质的半导体器件（例如MOSFET晶体管）的制造期间抑制次氧化物形成的系统和方法。在一个示例中，MOSFET晶体管包括包括高k栅极电介质和栅电极的栅极结构。在该示例中，栅极结构覆盖有用于在处理期间防止氧气进入结构的氮化物层，但是其足够薄以对加工有效地透明。

10. 发明申请

US20060131672A1 Nitrogen treatment to improve high-k gate dielectrics 有权
标题翻译：氮处理改善高k栅极电介质
公开(公告)号：US20060131672A1
公开(公告)日：2006-06-22
申请号：US11115932
申请日：2005-04-27
申请人： Chih-Hao Wang , Ta-Wei Wang , Shang-Chih Chen , Ching-Wei Tsai
发明人： Chih-Hao Wang , Ta-Wei Wang , Shang-Chih Chen , Ching-Wei Tsai
IPC分类号： H01L29/94
CPC分类号： H01L21/823462 , H01L21/28202 , H01L21/76829 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A MOSFET having a nitrided gate dielectric and its manufacture are disclosed. The method comprises providing a substrate and depositing a non-high-k dielectric material on the substrate. The non-high-k dielectric comprises two layers. The first layer adjacent the substrate is essentially nitrogen-free, and the second layer includes between about 1015 atoms/cm3 to about 1022 atoms/cm3 nitrogen. The MOSFET further includes a high-k dielectric material on the nitrided, non-high-k dielectric. The high-k dielectric preferably includes HfSiON, ZrSiON, or nitrided Al2O3. Embodiments further include asymmetric manufacturing techniques wherein core and peripheral integrated circuit areas are separately optimized.
摘要翻译：公开了具有氮化栅极电介质的MOSFET及其制造。该方法包括提供衬底并在衬底上沉积非高k电介质材料。非高k电介质包括两层。与衬底相邻的第一层基本上是无氮的，而第二层包含约10 15个原子/ cm 3至约10 22个/ 原子/ cm 3氮气。 MOSFET还包括在氮化的非高k电介质上的高k电介质材料。高k电介质优选包括HfSiON，ZrSiON或氮化的Al 2 O 3 N 3。实施例还包括其中核心和外围集成电路区域被分开优化的不对称制造技术。

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