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1. 发明授权

US5742842A Data processing apparatus for executing a vector operation under control of a master processor 失效
标题翻译：数据处理装置，用于在主处理器的控制下执行向量操作
公开(公告)号：US5742842A
公开(公告)日：1998-04-21
申请号：US601704
申请日：1996-02-15
申请人： Seiji Suetake , Hideyuki Iino , Koichi Hatta , Tatsuya Nagasawa , Koichi Kuroiwa , Hiroyuki Fujiyama , Kenji Shirasawa , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
发明人： Seiji Suetake , Hideyuki Iino , Koichi Hatta , Tatsuya Nagasawa , Koichi Kuroiwa , Hiroyuki Fujiyama , Kenji Shirasawa , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
IPC分类号： G06F9/38 , G06F15/78
CPC分类号： G06F9/3887 , G06F15/8053 , G06F9/30036 , G06F9/3877
摘要： A slave processor for executing for example a vector operation is connected to a master processor. A vector length for a vector operation set to the slave processor can be changed without intervention of the master processor. When the master processor activates the slave processor, the slave processor outputs a busy signal immediately (at most one cycle later). The master processor reads the value of a busy register representing a busy/ready status of the slave processor in a slave access cycle at highest speed (in two cycles at most). Regardless of whether the master processor and the slave processor was designed as series products or general purpose products, they can be effectively connected.
摘要翻译：用于执行例如向量操作的从属处理器连接到主处理器。可以在没有主处理器干预的情况下改变设置到从属处理器的向量操作的向量长度。当主处理器激活从属处理器时，从属处理器立即输出忙信号（最多一个周期）。主处理器以最高速度（最多两个周期）在从站访问周期中读取表示从属处理器的忙/就绪状态的忙寄存器的值。无论主处理器和从属处理器是设计为系列产品还是通用产品，都可以有效连接。

2. 发明授权

US5809552A Data processing system, memory access device and method including selecting the number of pipeline stages based on pipeline conditions 失效
标题翻译：数据处理系统，存储器访问装置和方法，包括基于流水线条件选择流水线级数
公开(公告)号：US5809552A
公开(公告)日：1998-09-15
申请号：US705562
申请日：1996-08-29
申请人： Koichi Kuroiwa , Hideyuki Iino , Hiroyuki Fujiyama , Kenji Shirasawa , Masaharu Kimura , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
发明人： Koichi Kuroiwa , Hideyuki Iino , Hiroyuki Fujiyama , Kenji Shirasawa , Masaharu Kimura , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
IPC分类号： G06F13/16 , G06F13/00
CPC分类号： G06F13/1615
摘要： A memory accessing device and method, in a data processing system which has pipelines, for correctly associating prefetched addresses from an address bus with corresponding prefetched data from a data bus, when sending data to and receiving data from an external memory. The memory accessing device has a condition determining device determining pipeline control conditions based on pipeline information and address information; a number-of-stages selecting device selecting the number of pipeline stages based on pipeline activation conditions and the pipeline control conditions; and a valid data detecting device detecting valid data positions in the prefetched data based on the number of pipeline stages selected and correctly associating the valid data positions in the prefetched data with the prefetched addresses. Additionally, a data input/output unit performs an arithmetic operation on data transferred from an external memory to a vector register, wherein the result of the arithmetic operation, upon completion, is transferred from the vector register to the external memory for storage. The data input/output unit has a data holding unit storing m-bit data units and rearranges exactly in the original order n pieces of m/n-bit data when n pieces of m/n-bit data are loaded from an external memory and then stored back into the external memory.
摘要翻译：一种具有管线的数据处理系统中的存储器访问装置和方法，用于当从外部存储器发送数据并从外部存储器接收数据时，将来自地址总线的预取地址与来自数据总线的相应预取数据正确地相关联。所述存储器访问装置具有根据流水线信息和地址信息确定流水线控制条件的条件判定装置; 阶段选择装置，其基于流水线激活条件和流水线控制条件选择流水线级数; 以及有效数据检测装置，基于所选择的流水线级数，并将预取数据中的有效数据位置与预取地址正确地相关联，来检测预取数据中的有效数据位置。此外，数据输入/输出单元对从外部存储器传送到向量寄存器的数据执行算术运算，其中算术运算的结果在完成后从矢量寄存器传送到外部存储器用于存储。数据输入/输出单元具有存储m位数据单元的数据保持单元，并且当从外部存储器加载n个m / n位数据时，以原始顺序重新排列n个m / n位数据，然后存储回外部存储器。

3. 发明授权

US5699553A Memory accessing device for a pipeline information processing system 失效
标题翻译：管道信息处理系统的存储器访问设备
公开(公告)号：US5699553A
公开(公告)日：1997-12-16
申请号：US988596
申请日：1992-12-10
申请人： Hideyuki Iino , Hiromasa Takahashi , Hiroyuki Fujiyama , Koichi Kuroiwa , Kenji Shirasawa
发明人： Hideyuki Iino , Hiromasa Takahashi , Hiroyuki Fujiyama , Koichi Kuroiwa , Kenji Shirasawa
IPC分类号： G06F13/16 , G06F13/364 , G06F13/18 , G06F12/10
CPC分类号： G06F13/364 , G06F13/1605 , G06F13/1615
摘要： A memory accessing device is connected to a central processing unit and a memory unit via a common bus. The memory accessing device accesses the memory unit independently of the central processing unit. The device includes an address generating unit for generating an address, an address control unit for outputting the generated address to the bus, and a control unit for controlling the address control unit to suspend or terminate memory access controlled in an address pipeline mode when the memory accessing device internally or externally issues a request for the suspension or the termination of the memory access controlled in the address pipeline mode. The control unit terminates or suspends the memory access when it receives a request internally or externally of the memory accessing device for the suspension or the termination of the memory access.
摘要翻译：存储器访问设备经由公共总线连接到中央处理单元和存储器单元。存储器访问设备独立于中央处理单元访问存储器单元。该设备包括用于产生地址的地址生成单元，用于向总线输出所生成的地址的地址控制单元，以及控制单元，用于在存储器中控制地址控制单元暂停或终止在地址流水线模式下控制的存储器访问在内部或外部访问设备发出对在地址管道模式中控制的存储器访问的暂停或终止的请求。当控制单元在存储器访问设备的内部或外部接收到用于暂停或终止存储器访问的请求时，终止或暂停存储器访问。

4. 发明授权

US06839811B2 Semaphore management circuit 有权
标题翻译：信号管理电路
公开(公告)号：US06839811B2
公开(公告)日：2005-01-04
申请号：US10092306
申请日：2002-03-07
申请人： Hiroyuki Fujiyama
发明人： Hiroyuki Fujiyama
IPC分类号： G06F15/177 , G06F9/46 , G06F9/52 , G06F12/00
CPC分类号： G06F9/526
摘要： A circuit includes a register which stores therein a semaphore address, and further includes a semaphore control circuit which asserts a control signal in response to a read access by a processor directed to the semaphore address, and negates the control signal in response to a write access by the processor directed to the semaphore address.

5. 发明授权

US6078202A Semiconductor device having portions that operate at different frequencies, and method of designing the device 有权
标题翻译：具有以不同频率工作的部分的半导体器件，以及设计该器件的方法
公开(公告)号：US6078202A
公开(公告)日：2000-06-20
申请号：US134518
申请日：1998-08-14
申请人： Hideaki Tomatsuri , Hiroyuki Fujiyama , Noriaki Ono , Minoru Usui
发明人： Hideaki Tomatsuri , Hiroyuki Fujiyama , Noriaki Ono , Minoru Usui
IPC分类号： G06F1/06 , G06F1/12 , H03L7/00
CPC分类号： G06F1/12 , H03L7/00
摘要： Disclosed are a semiconductor device of which a block having a plurality of portions that operate based on a plurality of clocks can be designed and inspected easily, and a method of designing the semiconductor device. First and second clocks whose frequencies are mutually different are used to generate an enabling signal that is validated only during a short period including a transition edge of the second clock. The enabling signal and first clock are supplied to the second portion. The second portion synthesizes the enabling signal and first clock to substantially generate the second clock. Thus, the second portion is regarded as a portion that operates synchronously with the first clock.
摘要翻译：公开了一种半导体器件，其中可以容易地设计和检查具有基于多个时钟操作的多个部分的块，以及设计半导体器件的方法。其频率相互不同的第一和第二时钟用于产生仅在包括第二时钟的过渡沿的短周期期间被验证的使能信号。使能信号和第一时钟被提供给第二部分。第二部分合成使能信号和第一时钟以基本上产生第二时钟。因此，第二部分被认为是与第一时钟同步操作的部分。

6. 发明申请

US20080064368A1 Communication device and communication system 有权
标题翻译：通信设备和通信系统
公开(公告)号：US20080064368A1
公开(公告)日：2008-03-13
申请号：US11798304
申请日：2007-05-11
申请人： Hiroyoshi Yamashita , Hiroyuki Fujiyama
发明人： Hiroyoshi Yamashita , Hiroyuki Fujiyama
IPC分类号： H04M1/66
CPC分类号： H04W12/06 , H04W74/0866 , H04W88/18
摘要： A communication device capable of preventing interference due to collision of signals of a plurality of communication devices (slaves) is provided. The communication device characterized by having a receiving part which receives a request signal by radio, a counter which starts count of a count value on reception of the request signal, a comparing part which compares the count value and a comparison value, and a transmitting part which transmits an acknowledge signal by radio in accordance with a result of the comparison is provided.
摘要翻译：提供能够防止由于多个通信设备（从站）的信号的冲突引起的干扰的通信设备。所述通信装置的特征在于，具有通过无线电接收请求信号的接收部，开始接收请求信号时的计数值的计数的计数器，比较计数值和比较值的比较部，以及发送部提供了根据比较结果通过无线电发送确认信号的装置。

7. 发明授权

US5146595A Grouping device for forming input signals into groups 失效
标题翻译：用于形成输入信号到组中的分组设备
公开(公告)号：US5146595A
公开(公告)日：1992-09-08
申请号：US267862
申请日：1988-11-07
申请人： Hiroyuki Fujiyama , Kouichi Kuroiwa , Shinji Nishikawa , Hidetoshi Shimura , Shinji Oyamada
发明人： Hiroyuki Fujiyama , Kouichi Kuroiwa , Shinji Nishikawa , Hidetoshi Shimura , Shinji Oyamada
IPC分类号： G06F13/14 , G06F13/10 , G06F13/26
CPC分类号： G06F13/26
摘要： A grouping device comprises a register table and a grouping unit the register table having m registers corresponding to m groups, each register including an n-bits data storing portion corresponding to the n input signals, for registering relationships between the n input signals and the m groups, the grouping unit receiving grouping signals output from the register table and the n input signals, for selecting one group from the m groups for each input signal and grouping each input signal into the selected group in accordance with the register table. Therefore, the register access time is shortened and the confirmation of the contents of the register by the CPU is made easier.

8. 发明授权

US08588743B2 Communication device and communication system 有权
标题翻译：通信设备和通信系统
公开(公告)号：US08588743B2
公开(公告)日：2013-11-19
申请号：US11798304
申请日：2007-05-11
申请人： Hiroyoshi Yamashita , Hiroyuki Fujiyama
发明人： Hiroyoshi Yamashita , Hiroyuki Fujiyama
IPC分类号： H04M1/66
CPC分类号： H04W12/06 , H04W74/0866 , H04W88/18
摘要： A communication device capable of preventing interference due to collision of signals of a plurality of communication devices (slaves) is provided. The communication device characterized by having a receiving part which receives a request signal by radio, a counter which starts count of a count value on reception of the request signal, a comparing part which compares the count value and a comparison value, and a transmitting part which transmits an acknowledge signal by radio in accordance with a result of the comparison is provided.
摘要翻译：提供能够防止由于多个通信设备（从站）的信号的冲突引起的干扰的通信设备。所述通信装置的特征在于，具有通过无线电接收请求信号的接收部，开始接收请求信号时的计数值的计数的计数器，比较计数值和比较值的比较部，以及发送部提供了根据比较结果通过无线电发送确认信号的装置。

9. 发明授权

US06292861B1 Processor having interface with bus arbitration circuit 失效
标题翻译：处理器具有与总线仲裁电路的接口
公开(公告)号：US06292861B1
公开(公告)日：2001-09-18
申请号：US09294340
申请日：1999-04-20
申请人： Hiroyuki Fujiyama
发明人： Hiroyuki Fujiyama
IPC分类号： G06F13364
CPC分类号： G06F13/364
摘要： A processor 11A comprises a processor core 11 connected to an internal bus 14, an interface circuit 12 connected between the internal bus 14 and an external bus 22, and an interface circuit 13 connected between the internal bus 14 and an external bus 24. To simplify bus arbitration, the interface circuit 12 holds an address on the internal bus 14 in an first address buffer register 121 in response to an internal address strobe signal *ASi, judges based on the address value whether or not an access request is performed, outputs a bus request signal *PREQ, outputs the content of the first address register 121 onto the external bus 22 after getting a bus ownership, thereafter provides the data on the external bus 22 to the internal bus 14, and provides an internal ready signal *RDYi to the processor core 11. The processor may comprise a between-interface control circuit to enable to connect between the external circuits 22 and 24 in common.
摘要翻译：处理器11A包括连接到内部总线14的处理器核心11，连接在内部总线14和外部总线22之间的接口电路12以及连接在内部总线14和外部总线24之间的接口电路13.为了简化总线仲裁，接口电路12响应于内部地址选通信号* ASi在第一地址缓冲寄存器121中的内部总线14上保存地址，基于地址值判断是否执行访问请求，输出总线请求信号* PREQ在获得总线所有权之后将第一地址寄存器121的内容输出到外部总线22上，然后将外部总线22上的数据提供给内部总线14，并将内部就绪信号* RDYi提供给处理器核心11.处理器可以包括能够共同地在外部电路22和24之间连接的接口间控制电路。

10. 发明授权

US6009493A Data transfer control method and apparatus for performing consecutive burst transfer operations with a simple structure 失效
标题翻译：用于以简单的结构执行连续的突发传送操作的数据传送控制方法和装置
公开(公告)号：US6009493A
公开(公告)日：1999-12-28
申请号：US824761
申请日：1997-03-26
申请人： Hiroyuki Fujiyama
发明人： Hiroyuki Fujiyama
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F13/28
摘要： A method and apparatus for controlling transfer of data in which a plurality of burst transfer operations starting from an arbitrary byte as a start address are performed consecutively without a high-speed adder provided in the conventional data transfer apparatus performing burst transfer. Data is transferred between memories by a plurality of consecutive burst transfer operations performed on data stored in consecutive addresses. Each of the burst transfer operations is performed on the data stored in a respective one of memory cell areas each of which corresponds to a unit of burst transfer. A first address representing an address of one of the memory cell areas storing data to be transferred is calculated. The first address is a part of a start address of a second or later burst transfer operation. A second address representing an address of one of memory cells provided in the one of the memory cell areas is calculated separately. The data transfer operation is started from the one of the memory cells. The second address is a part of the start address of the second or later burst transfer operation.
摘要翻译：一种用于控制数据传送的方法和装置，其中从任意字节开始的多个突发传送操作作为起始地址连续执行，而不需要在执行突发传送的常规数据传送装置中提供的高速加法器。数据通过对存储在连续地址中的数据执行的多个连续的突发传送操作在存储器之间传送。每个突发传送操作对存储在相应的一个存储单元区域中的数据执行，每个存储单元区域对应于突发传送单元。计算表示存储要传送的数据的存储单元区域之一的地址的第一地址。第一个地址是第二次或以后的突发传送操作的起始地址的一部分。分别计算表示在一个存储单元区域中提供的一个存储单元的地址的第二地址。从存储单元之一开始数据传送操作。第二个地址是第二次或之后的突发传送操作的起始地址的一部分。

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