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1. 发明授权

US5146595A Grouping device for forming input signals into groups 失效
标题翻译：用于形成输入信号到组中的分组设备
公开(公告)号：US5146595A
公开(公告)日：1992-09-08
申请号：US267862
申请日：1988-11-07
申请人： Hiroyuki Fujiyama , Kouichi Kuroiwa , Shinji Nishikawa , Hidetoshi Shimura , Shinji Oyamada
发明人： Hiroyuki Fujiyama , Kouichi Kuroiwa , Shinji Nishikawa , Hidetoshi Shimura , Shinji Oyamada
IPC分类号： G06F13/14 , G06F13/10 , G06F13/26
CPC分类号： G06F13/26
摘要： A grouping device comprises a register table and a grouping unit the register table having m registers corresponding to m groups, each register including an n-bits data storing portion corresponding to the n input signals, for registering relationships between the n input signals and the m groups, the grouping unit receiving grouping signals output from the register table and the n input signals, for selecting one group from the m groups for each input signal and grouping each input signal into the selected group in accordance with the register table. Therefore, the register access time is shortened and the confirmation of the contents of the register by the CPU is made easier.

2. 发明授权

US5119496A Method and apparatus for interrupt processing in a computer system having peripheral units connected in a daisy chain 失效
标题翻译：具有连接在一个连接链上的外围设备的计算机系统中断处理的方法和装置
公开(公告)号：US5119496A
公开(公告)日：1992-06-02
申请号：US282778
申请日：1988-12-12
申请人： Sinji Nishikawa , Hiroyuki Fujiyama , Kouichi Kuroiwa , Shinji Oyamada , Hidetoshi Shimura
发明人： Sinji Nishikawa , Hiroyuki Fujiyama , Kouichi Kuroiwa , Shinji Oyamada , Hidetoshi Shimura
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An interrupt processing method and an interrupt processing apparatus provides an end indicative information storing unit for storing an end indicative information of a daisy chain for at least one of a plurality peripheral units, the peripheral unit receiving the indicative information when the peripheral unit receives an acknowledge signal but does not output a request signal, and the peripheral unit outputs a specific chain end state signal to the central processing unit, so that the central processing unit is returned from a response waiting state. Therefore, when an error request signal is produced by noise, etc., delay at a central processing unit is reduced. Further, the daisy chain connection is cut at an optional portion and a request signal from an irrevelant peripheral unit is ignored, so that the efficiency of the processing is improved.

3. 发明授权

US5655114A System and device for prefetching command and parameters to be processed with least frequent bus access 失效
标题翻译：用于预取命令和参数的系统和设备，以最少频繁的总线访问进行处理
公开(公告)号：US5655114A
公开(公告)日：1997-08-05
申请号：US453475
申请日：1995-05-30
申请人： Takayoshi Taniai , Hajime Sato , Hidetoshi Shimura , Tadashi Saitoh , Shinji Oyamada
发明人： Takayoshi Taniai , Hajime Sato , Hidetoshi Shimura , Tadashi Saitoh , Shinji Oyamada
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/3802 , G06F9/3814 , G06F9/383
摘要： A data processing device contains art execution circuit and a data buffer circuit which stores one or more commands and/or one or more parameters which are prefetched, until each of the commands and parameters is read out by the execution circuit. The execution circuit inputs the oldest command stored in the data buffer circuit when an execution of a preceding command is completed, inputs one or more parameters stored in the data buffer circuit when the command input therein requests the parameters, and executes the command input therein, using the parameters when the parameters are input therein. The device further contains a circuit for detecting whether or not there is enough vacant space in the data buffer circuit in which a further command and/or a parameter can be stored, and another circuit for detecting a state of the data buffer circuit in which state the data buffer circuit does not store data including a command and/or a parameter, which is necessary for a next operation in the execution circuit. A prefetch control circuit, provided in either in the device or outside of the device, starts the prefetch operation and continues successive prefetch operations when the second state is detected, and stops the prefetch operation when the first state is detected. The system using the device contains a memory which stores the commands and parameters in the order of execution in the execution circuit.
摘要翻译：数据处理装置包含艺术执行电路和存储一个或多个命令的数据缓冲器电路和/或预取的一个或多个参数，直到执行电路读出每个命令和参数为止。当执行前一个命令完成时，执行电路输入存储在数据缓冲器电路中的最早的命令，当输入其中的命令请求参数时输入存储在数据缓冲器电路中的一个或多个参数，并执行其中输入的命令，当输入参数时使用参数。该装置还包括用于检测数据缓冲器电路中是否存在足够的空闲空间的电路，其中可以存储另外的命令和/或参数，以及用于检测其中状态的数据缓冲器电路的状态的另一电路数据缓冲电路不存储包括执行电路中的下一个操作所必需的命令和/或参数的数据。设置在设备中或设备外部的预取控制电路在检测到第二状态时开始预取操作并继续连续预取操作，并且当检测到第一状态时停止预取操作。使用该装置的系统包含以执行电路中的执行顺序存储命令和参数的存储器。

4. 发明授权

US5463740A Data control device generating different types of bus requests and transmitting requests directly to one of a number of arbiters for obtaining access to a respective bus 失效
标题翻译：数据控制装置产生不同类型的总线请求，并将请求直接发送到多个仲裁器中的一个以获得对各自总线的访问
公开(公告)号：US5463740A
公开(公告)日：1995-10-31
申请号：US387633
申请日：1995-02-13
申请人： Takayoshi Taniai , Hajime Satoh , Hidetoshi Shimura , Tadashi Saitoh
发明人： Takayoshi Taniai , Hajime Satoh , Hidetoshi Shimura , Tadashi Saitoh
IPC分类号： G06F13/36 , G06F13/362 , G06F13/00 , G06F13/14
CPC分类号： G06F13/36 , G06F13/362
摘要： A data control device which acquires the right to use a bus and performs data control includes a request circuit which selectively generates a plurality of request signals for acquiring the right to use corresponding buses. The plurality of request signals are based on attributes of data to be exchanged with an external device. The exchanged data includes data and commands.
摘要翻译：获取使用总线并执行数据控制的权利的数据控制装置包括选择性地生成用于获取使用相应总线的权利的多个请求信号的请求电路。多个请求信号基于要与外部设备交换的数据的属性。交换的数据包括数据和命令。

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