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1. 发明授权

US5742842A Data processing apparatus for executing a vector operation under control of a master processor 失效
标题翻译：数据处理装置，用于在主处理器的控制下执行向量操作
公开(公告)号：US5742842A
公开(公告)日：1998-04-21
申请号：US601704
申请日：1996-02-15
申请人： Seiji Suetake , Hideyuki Iino , Koichi Hatta , Tatsuya Nagasawa , Koichi Kuroiwa , Hiroyuki Fujiyama , Kenji Shirasawa , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
发明人： Seiji Suetake , Hideyuki Iino , Koichi Hatta , Tatsuya Nagasawa , Koichi Kuroiwa , Hiroyuki Fujiyama , Kenji Shirasawa , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
IPC分类号： G06F9/38 , G06F15/78
CPC分类号： G06F9/3887 , G06F15/8053 , G06F9/30036 , G06F9/3877
摘要： A slave processor for executing for example a vector operation is connected to a master processor. A vector length for a vector operation set to the slave processor can be changed without intervention of the master processor. When the master processor activates the slave processor, the slave processor outputs a busy signal immediately (at most one cycle later). The master processor reads the value of a busy register representing a busy/ready status of the slave processor in a slave access cycle at highest speed (in two cycles at most). Regardless of whether the master processor and the slave processor was designed as series products or general purpose products, they can be effectively connected.
摘要翻译：用于执行例如向量操作的从属处理器连接到主处理器。可以在没有主处理器干预的情况下改变设置到从属处理器的向量操作的向量长度。当主处理器激活从属处理器时，从属处理器立即输出忙信号（最多一个周期）。主处理器以最高速度（最多两个周期）在从站访问周期中读取表示从属处理器的忙/就绪状态的忙寄存器的值。无论主处理器和从属处理器是设计为系列产品还是通用产品，都可以有效连接。

2. 发明授权

US5809552A Data processing system, memory access device and method including selecting the number of pipeline stages based on pipeline conditions 失效
标题翻译：数据处理系统，存储器访问装置和方法，包括基于流水线条件选择流水线级数
公开(公告)号：US5809552A
公开(公告)日：1998-09-15
申请号：US705562
申请日：1996-08-29
申请人： Koichi Kuroiwa , Hideyuki Iino , Hiroyuki Fujiyama , Kenji Shirasawa , Masaharu Kimura , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
发明人： Koichi Kuroiwa , Hideyuki Iino , Hiroyuki Fujiyama , Kenji Shirasawa , Masaharu Kimura , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
IPC分类号： G06F13/16 , G06F13/00
CPC分类号： G06F13/1615
摘要： A memory accessing device and method, in a data processing system which has pipelines, for correctly associating prefetched addresses from an address bus with corresponding prefetched data from a data bus, when sending data to and receiving data from an external memory. The memory accessing device has a condition determining device determining pipeline control conditions based on pipeline information and address information; a number-of-stages selecting device selecting the number of pipeline stages based on pipeline activation conditions and the pipeline control conditions; and a valid data detecting device detecting valid data positions in the prefetched data based on the number of pipeline stages selected and correctly associating the valid data positions in the prefetched data with the prefetched addresses. Additionally, a data input/output unit performs an arithmetic operation on data transferred from an external memory to a vector register, wherein the result of the arithmetic operation, upon completion, is transferred from the vector register to the external memory for storage. The data input/output unit has a data holding unit storing m-bit data units and rearranges exactly in the original order n pieces of m/n-bit data when n pieces of m/n-bit data are loaded from an external memory and then stored back into the external memory.
摘要翻译：一种具有管线的数据处理系统中的存储器访问装置和方法，用于当从外部存储器发送数据并从外部存储器接收数据时，将来自地址总线的预取地址与来自数据总线的相应预取数据正确地相关联。所述存储器访问装置具有根据流水线信息和地址信息确定流水线控制条件的条件判定装置; 阶段选择装置，其基于流水线激活条件和流水线控制条件选择流水线级数; 以及有效数据检测装置，基于所选择的流水线级数，并将预取数据中的有效数据位置与预取地址正确地相关联，来检测预取数据中的有效数据位置。此外，数据输入/输出单元对从外部存储器传送到向量寄存器的数据执行算术运算，其中算术运算的结果在完成后从矢量寄存器传送到外部存储器用于存储。数据输入/输出单元具有存储m位数据单元的数据保持单元，并且当从外部存储器加载n个m / n位数据时，以原始顺序重新排列n个m / n位数据，然后存储回外部存储器。

3. 发明授权

US5699553A Memory accessing device for a pipeline information processing system 失效
标题翻译：管道信息处理系统的存储器访问设备
公开(公告)号：US5699553A
公开(公告)日：1997-12-16
申请号：US988596
申请日：1992-12-10
申请人： Hideyuki Iino , Hiromasa Takahashi , Hiroyuki Fujiyama , Koichi Kuroiwa , Kenji Shirasawa
发明人： Hideyuki Iino , Hiromasa Takahashi , Hiroyuki Fujiyama , Koichi Kuroiwa , Kenji Shirasawa
IPC分类号： G06F13/16 , G06F13/364 , G06F13/18 , G06F12/10
CPC分类号： G06F13/364 , G06F13/1605 , G06F13/1615
摘要： A memory accessing device is connected to a central processing unit and a memory unit via a common bus. The memory accessing device accesses the memory unit independently of the central processing unit. The device includes an address generating unit for generating an address, an address control unit for outputting the generated address to the bus, and a control unit for controlling the address control unit to suspend or terminate memory access controlled in an address pipeline mode when the memory accessing device internally or externally issues a request for the suspension or the termination of the memory access controlled in the address pipeline mode. The control unit terminates or suspends the memory access when it receives a request internally or externally of the memory accessing device for the suspension or the termination of the memory access.
摘要翻译：存储器访问设备经由公共总线连接到中央处理单元和存储器单元。存储器访问设备独立于中央处理单元访问存储器单元。该设备包括用于产生地址的地址生成单元，用于向总线输出所生成的地址的地址控制单元，以及控制单元，用于在存储器中控制地址控制单元暂停或终止在地址流水线模式下控制的存储器访问在内部或外部访问设备发出对在地址管道模式中控制的存储器访问的暂停或终止的请求。当控制单元在存储器访问设备的内部或外部接收到用于暂停或终止存储器访问的请求时，终止或暂停存储器访问。

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