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1. 发明授权

US06631433B1 Bus arbiter for a data storage system 有权
标题翻译：总线仲裁器，用于数据存储系统
公开(公告)号：US06631433B1
公开(公告)日：2003-10-07
申请号：US09670709
申请日：2000-09-27
申请人： Nicholas Paluzzi
发明人： Nicholas Paluzzi
IPC分类号： G06F13364
CPC分类号： G06F13/364
摘要： A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives. The method includes transferring messages through a messaging network with the data being transferred between the host computer/server and the bank of disk drives through a cache memory, such message network being independent of the cache memory.
摘要翻译：系统接口包括多个第一导向器，多个第二导向器，数据传输部分和消息网络。数据传送部分包括高速缓冲存储器。高速缓存存储器耦合到多个第一和第二导向器。消息传递网络独立于数据传送部分运行，并且这样的网络耦合到多个第一董事和多个第二董事。第一和第二位董事通过消息传递网络响应第一任董事和第二任董事之间的信息，控制第一任董事与第二任董事之间的数据转移，以促进第一任董事与第二任董事之间的数据转移。数据通过数据传输部分的高速缓冲存储器。一种用于操作适于在主计算机/服务器和一组磁盘驱动器之间传送数据的数据存储系统的方法。该方法包括通过消息传递网络传送消息，数据通过高速缓冲存储器在主机计算机/服务器和磁盘驱动器组之间传输，这样的消息网络独立于高速缓冲存储器。

2. 发明授权

US06292861B1 Processor having interface with bus arbitration circuit 失效
标题翻译：处理器具有与总线仲裁电路的接口
公开(公告)号：US06292861B1
公开(公告)日：2001-09-18
申请号：US09294340
申请日：1999-04-20
申请人： Hiroyuki Fujiyama
发明人： Hiroyuki Fujiyama
IPC分类号： G06F13364
CPC分类号： G06F13/364
摘要： A processor 11A comprises a processor core 11 connected to an internal bus 14, an interface circuit 12 connected between the internal bus 14 and an external bus 22, and an interface circuit 13 connected between the internal bus 14 and an external bus 24. To simplify bus arbitration, the interface circuit 12 holds an address on the internal bus 14 in an first address buffer register 121 in response to an internal address strobe signal *ASi, judges based on the address value whether or not an access request is performed, outputs a bus request signal *PREQ, outputs the content of the first address register 121 onto the external bus 22 after getting a bus ownership, thereafter provides the data on the external bus 22 to the internal bus 14, and provides an internal ready signal *RDYi to the processor core 11. The processor may comprise a between-interface control circuit to enable to connect between the external circuits 22 and 24 in common.
摘要翻译：处理器11A包括连接到内部总线14的处理器核心11，连接在内部总线14和外部总线22之间的接口电路12以及连接在内部总线14和外部总线24之间的接口电路13.为了简化总线仲裁，接口电路12响应于内部地址选通信号* ASi在第一地址缓冲寄存器121中的内部总线14上保存地址，基于地址值判断是否执行访问请求，输出总线请求信号* PREQ在获得总线所有权之后将第一地址寄存器121的内容输出到外部总线22上，然后将外部总线22上的数据提供给内部总线14，并将内部就绪信号* RDYi提供给处理器核心11.处理器可以包括能够共同地在外部电路22和24之间连接的接口间控制电路。

3. 发明授权

US06463524B1 Superscalar processor and method for incrementally issuing store instructions 失效
标题翻译：超标量处理器和递增发出存储指令的方法
公开(公告)号：US06463524B1
公开(公告)日：2002-10-08
申请号：US09383607
申请日：1999-08-26
申请人： Maureen Delaney , Hung Qui Le , Dung Quoc Nguyen , Robert McDonald , David W. Victor
发明人： Maureen Delaney , Hung Qui Le , Dung Quoc Nguyen , Robert McDonald , David W. Victor
IPC分类号： G06F13364
CPC分类号： G06F9/3017 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A superscalar processor and method are disclosed for efficiently executing a store instruction. The store instruction is stored in an issue queue within the processor. A first part of the store instruction is issued from the issue queue to a first one of different execution units in response to a first operand becoming available. A second part of the store instruction is issued from the issue queue to a second one of the different execution units in response to a second operand becoming available. The store instruction is completed in response to executing the first part of the store instruction by the first one of the execution units and the second part of the store instruction by the second one of the execution units.
摘要翻译：公开了一种用于有效执行存储指令的超标量处理器和方法。存储指令存储在处理器内的问题队列中。响应于第一操作数变得可用，存储指令的第一部分从发布队列发送到不同执行单元中的第一个。响应于第二操作数变得可用，存储指令的第二部分从发布队列发送到不同执行单元中的第二部分。存储指令响应于由第一执行单元执行存储指令的第一部分和由第二执行单元执行存储指令的第二部分。

4. 发明授权

US06311263B1 Data processing circuits and interfaces 失效
标题翻译：数据处理电路和接口
公开(公告)号：US06311263B1
公开(公告)日：2001-10-30
申请号：US08809498
申请日：1997-03-24
申请人： Stephen John Barlow , Alistair Guy Morfey , James Digby Collier
发明人： Stephen John Barlow , Alistair Guy Morfey , James Digby Collier
IPC分类号： G06F13364
CPC分类号： G06F7/57 , G06F1/3203 , G06F1/3237 , G06F9/30 , G06F9/30014 , G06F9/30032 , G06F9/3005 , G06F9/30083 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/322 , G06F9/324 , G06F9/3869 , G06F11/2236 , G06F11/3648 , G06F11/3656 , G06F15/7832 , Y02D10/128 , Y02D50/20
摘要： An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analogue and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. External pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test data or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SER-CLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space of the processor core, without specific program control. Within each processor cycle, the processor circuitry is divided into plural stages, and latches are interposed between the stages to minimize power consumption.
摘要翻译：集成电路包含微处理器内核，程序存储器和单独的数据存储器，以及模拟和数字信号处理电路。 ALU为16位宽，但提供32位移位单元，使用一对16位寄存器。处理器具有固定长度的指令格式，其中指令集包括在多个周期内使用移位单元的乘法和除法运算。不提供中断。集成电路的外部引脚允许单步和其他调试操作，以及允许外部通信测试数据或工作数据的串行接口（SIF）。串行接口有四根线（SERIN，SEROUT，SER-CLK，SERLOADB），允许与主设备进行握手，并允许直接访问处理器内核的存储空间，无需特定的程序控制。在每个处理器周期内，处理器电路被分成多个级，并且锁存器插在两个级之间以使功耗最小化。

5. 发明授权

US06779120B1 Declarative language for specifying a security policy 有权
标题翻译：用于指定安全策略的声明语言
公开(公告)号：US06779120B1
公开(公告)日：2004-08-17
申请号：US09479781
申请日：2000-01-07
申请人： Luis Filipe Pereira Valente , Geoffrey Howard Cooper , Robert Allen Shaw , Kieran Gerard Sherlock
发明人： Luis Filipe Pereira Valente , Geoffrey Howard Cooper , Robert Allen Shaw , Kieran Gerard Sherlock
IPC分类号： G06F13364
CPC分类号： H04L41/50 , H04L41/0609 , H04L41/069 , H04L41/0893 , H04L41/22 , H04L63/0442 , H04L63/08 , H04L63/0823 , H04L63/1408 , H04L63/1433 , H04L63/166 , H04L63/20
摘要： The invention is a declarative language system and comprises a language as a tool for expressing network security policy in a formalized way. It allows the specification of security policy across a wide variety of networking layers and protocols. Using the language, a security administrator assigns a disposition to each and every network event that can occur in a data communications network. The event's disposition determines whether the event is allowed (i.e. conforms to the specified policy) or disallowed and what action, if any, should be taken by a system monitor in response to that event. Possible actions include, for example, logging the information into a database, notifying a human operator, and disrupting the offending network traffic.
摘要翻译：本发明是一种声明性语言系统，并且包括作为用于以正式方式表达网络安全策略的工具的语言。它允许通过各种各样的网络层和协议来规范安全策略。使用该语言，安全管理员将配置分配给可能发生在数据通信网络中的每个网络事件。事件的处置决定事件是允许的（即符合指定的策略）还是不允许的，并且响应于该事件应该由系统监视器采取什么动作（如果有的话）。可能的操作包括例如将信息记录到数据库中，通知人类操作者，以及中断违规的网络流量。

6. 发明授权

US06516369B1 Fair and high speed arbitration system based on rotative and weighted priority monitoring 失效
标题翻译：基于旋转和加权优先级监控的公平和高速仲裁系统
公开(公告)号：US06516369B1
公开(公告)日：2003-02-04
申请号：US09473496
申请日：1999-12-28
申请人： Francis G. Bredin
发明人： Francis G. Bredin
IPC分类号： G06F13364
CPC分类号： G06F13/364
摘要： A mixed rotative and weighted arbiter for arbitrating the priority of request signals R1-Rn supplied from a plurality of devices is disclosed. The arbiter is composed of a token circuit which delivers a token vector having one position set active. The token vector as well as the plurality of request signals are input to a rotative arbitration circuit. The rotative arbitration circuit processes a round robin algorithm to output a rotative request vector having input requests ordered from a higher to a lower priority configuration according to the active position of the token vector. The arbiter further comprises a weighted arbitration circuit connected to the output of the rotative arbitration circuit for generating a weighted request vector determining a linear priority configuration of the rotative request vector. A grant generation circuit is connected to the output of the weighted arbitration circuit and to the output of the token circuit to deliver a grant order to the device which may gain access to the bus and a plurality of no grant orders to the others devices.
摘要翻译：公开了一种用于仲裁从多个设备提供的请求信号R1-Rn的优先级的混合旋转和加权仲裁器。仲裁器由令牌电路组成，令牌电路传送一个位置设置为有效的令牌向量。令牌向量以及多个请求信号被输入到旋转仲裁电路。旋转仲裁电路处理循环算法以根据令牌向量的活动位置输出具有从较高优先级配置到低优先级配置排序的输入请求的旋转请求向量。仲裁器还包括连接到旋转仲裁电路的输出的加权仲裁电路，用于生成确定旋转请求向量的线性优先级配置的加权请求向量。授权生成电路连接到加权仲裁电路的输出和令牌电路的输出，以向授权订单提供授权订单给设备，该设备可以访问总线，并向其他设备发送多个无授权订单。

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