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1. 发明授权

US5699553A Memory accessing device for a pipeline information processing system 失效
标题翻译：管道信息处理系统的存储器访问设备
公开(公告)号：US5699553A
公开(公告)日：1997-12-16
申请号：US988596
申请日：1992-12-10
申请人： Hideyuki Iino , Hiromasa Takahashi , Hiroyuki Fujiyama , Koichi Kuroiwa , Kenji Shirasawa
发明人： Hideyuki Iino , Hiromasa Takahashi , Hiroyuki Fujiyama , Koichi Kuroiwa , Kenji Shirasawa
IPC分类号： G06F13/16 , G06F13/364 , G06F13/18 , G06F12/10
CPC分类号： G06F13/364 , G06F13/1605 , G06F13/1615
摘要： A memory accessing device is connected to a central processing unit and a memory unit via a common bus. The memory accessing device accesses the memory unit independently of the central processing unit. The device includes an address generating unit for generating an address, an address control unit for outputting the generated address to the bus, and a control unit for controlling the address control unit to suspend or terminate memory access controlled in an address pipeline mode when the memory accessing device internally or externally issues a request for the suspension or the termination of the memory access controlled in the address pipeline mode. The control unit terminates or suspends the memory access when it receives a request internally or externally of the memory accessing device for the suspension or the termination of the memory access.
摘要翻译：存储器访问设备经由公共总线连接到中央处理单元和存储器单元。存储器访问设备独立于中央处理单元访问存储器单元。该设备包括用于产生地址的地址生成单元，用于向总线输出所生成的地址的地址控制单元，以及控制单元，用于在存储器中控制地址控制单元暂停或终止在地址流水线模式下控制的存储器访问在内部或外部访问设备发出对在地址管道模式中控制的存储器访问的暂停或终止的请求。当控制单元在存储器访问设备的内部或外部接收到用于暂停或终止存储器访问的请求时，终止或暂停存储器访问。

2. 发明授权

US5742842A Data processing apparatus for executing a vector operation under control of a master processor 失效
标题翻译：数据处理装置，用于在主处理器的控制下执行向量操作
公开(公告)号：US5742842A
公开(公告)日：1998-04-21
申请号：US601704
申请日：1996-02-15
申请人： Seiji Suetake , Hideyuki Iino , Koichi Hatta , Tatsuya Nagasawa , Koichi Kuroiwa , Hiroyuki Fujiyama , Kenji Shirasawa , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
发明人： Seiji Suetake , Hideyuki Iino , Koichi Hatta , Tatsuya Nagasawa , Koichi Kuroiwa , Hiroyuki Fujiyama , Kenji Shirasawa , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
IPC分类号： G06F9/38 , G06F15/78
CPC分类号： G06F9/3887 , G06F15/8053 , G06F9/30036 , G06F9/3877
摘要： A slave processor for executing for example a vector operation is connected to a master processor. A vector length for a vector operation set to the slave processor can be changed without intervention of the master processor. When the master processor activates the slave processor, the slave processor outputs a busy signal immediately (at most one cycle later). The master processor reads the value of a busy register representing a busy/ready status of the slave processor in a slave access cycle at highest speed (in two cycles at most). Regardless of whether the master processor and the slave processor was designed as series products or general purpose products, they can be effectively connected.
摘要翻译：用于执行例如向量操作的从属处理器连接到主处理器。可以在没有主处理器干预的情况下改变设置到从属处理器的向量操作的向量长度。当主处理器激活从属处理器时，从属处理器立即输出忙信号（最多一个周期）。主处理器以最高速度（最多两个周期）在从站访问周期中读取表示从属处理器的忙/就绪状态的忙寄存器的值。无论主处理器和从属处理器是设计为系列产品还是通用产品，都可以有效连接。

3. 发明授权

US5809552A Data processing system, memory access device and method including selecting the number of pipeline stages based on pipeline conditions 失效
标题翻译：数据处理系统，存储器访问装置和方法，包括基于流水线条件选择流水线级数
公开(公告)号：US5809552A
公开(公告)日：1998-09-15
申请号：US705562
申请日：1996-08-29
申请人： Koichi Kuroiwa , Hideyuki Iino , Hiroyuki Fujiyama , Kenji Shirasawa , Masaharu Kimura , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
发明人： Koichi Kuroiwa , Hideyuki Iino , Hiroyuki Fujiyama , Kenji Shirasawa , Masaharu Kimura , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
IPC分类号： G06F13/16 , G06F13/00
CPC分类号： G06F13/1615
摘要： A memory accessing device and method, in a data processing system which has pipelines, for correctly associating prefetched addresses from an address bus with corresponding prefetched data from a data bus, when sending data to and receiving data from an external memory. The memory accessing device has a condition determining device determining pipeline control conditions based on pipeline information and address information; a number-of-stages selecting device selecting the number of pipeline stages based on pipeline activation conditions and the pipeline control conditions; and a valid data detecting device detecting valid data positions in the prefetched data based on the number of pipeline stages selected and correctly associating the valid data positions in the prefetched data with the prefetched addresses. Additionally, a data input/output unit performs an arithmetic operation on data transferred from an external memory to a vector register, wherein the result of the arithmetic operation, upon completion, is transferred from the vector register to the external memory for storage. The data input/output unit has a data holding unit storing m-bit data units and rearranges exactly in the original order n pieces of m/n-bit data when n pieces of m/n-bit data are loaded from an external memory and then stored back into the external memory.
摘要翻译：一种具有管线的数据处理系统中的存储器访问装置和方法，用于当从外部存储器发送数据并从外部存储器接收数据时，将来自地址总线的预取地址与来自数据总线的相应预取数据正确地相关联。所述存储器访问装置具有根据流水线信息和地址信息确定流水线控制条件的条件判定装置; 阶段选择装置，其基于流水线激活条件和流水线控制条件选择流水线级数; 以及有效数据检测装置，基于所选择的流水线级数，并将预取数据中的有效数据位置与预取地址正确地相关联，来检测预取数据中的有效数据位置。此外，数据输入/输出单元对从外部存储器传送到向量寄存器的数据执行算术运算，其中算术运算的结果在完成后从矢量寄存器传送到外部存储器用于存储。数据输入/输出单元具有存储m位数据单元的数据保持单元，并且当从外部存储器加载n个m / n位数据时，以原始顺序重新排列n个m / n位数据，然后存储回外部存储器。

4. 发明授权

US5654972A Processor having test circuit 失效
标题翻译：处理器有测试电路
公开(公告)号：US5654972A
公开(公告)日：1997-08-05
申请号：US226854
申请日：1994-04-13
申请人： Koichi Kuroiwa , Hideyuki Iino
发明人： Koichi Kuroiwa , Hideyuki Iino
IPC分类号： G06F11/22 , G06F11/267 , G06F15/78 , G06F11/00
CPC分类号： G06F11/2236
摘要： A processor includes a register file unit for storing operands and operation results, operation units for performing operations on the operands and writing operation results into the register file unit in a normal operation mode, and a random number generator for generating random numbers and outputting, instead of the operands, the random numbers to the operation units in a test mode. Further, the processor includes a selector part for selecting the operands from the register file unit in the normal operation mode and selecting the random numbers generated by the random number generator in the test mode, the operands or the random numbers selected by said selector being applied to the operation units.
摘要翻译：处理器包括用于存储操作数和操作结果的寄存器文件单元，用于对操作数执行操作的操作单元和以正常操作模式将操作结果写入寄存器文件单元，以及用于产生随机数并随后输出的随机数生成器的操作数，在测试模式下的操作单元的随机数。此外，处理器包括：选择器部分，用于在正常操作模式中从寄存器文件单元中选择操作数，并且在测试模式中选择由随机数生成器生成的随机数，由所述选择器选择的操作数或随机数被应用到操作单位。

5. 发明授权

US07573779B2 Semiconductor memory and electronic device 有权
标题翻译：半导体存储器和电子器件
公开(公告)号：US07573779B2
公开(公告)日：2009-08-11
申请号：US12000051
申请日：2007-12-07
申请人： Masami Kanasugi , Koichi Kuroiwa , Makoto Muranushi
发明人： Masami Kanasugi , Koichi Kuroiwa , Makoto Muranushi
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C5/14
摘要： A semiconductor memory that reduces the power consumption of a memory cell array without exercising control by a microprocessor. The semiconductor memory comprises a memory cell array, a switch for turning on/off power corresponding to row addresses of the memory cell array, an address control section for exercising sequence control on the basis of a write pointer (WP) generated at the time of a write signal being inputted for designating a row address to which data of a predetermined data stream is to be written and a read pointer (RP) generated at the time of a read signal being inputted for designating a row address from which the data is to be read out, and a switch signal output section for generating switch signals for controlling the switch on the basis of the WP and the RP.
摘要翻译：一种半导体存储器，其在不进行微处理器控制的情况下降低存储单元阵列的功耗。半导体存储器包括存储单元阵列，用于接通/关断与存储单元阵列的行地址相对应的功率的开关，用于根据在第一时钟产生的写指针（WP）进行序列控制的地址控制部分，输入写入信号，用于指定要写入预定数据流的数据的行地址和在输入读取信号时生成的读取指针（RP），用于指定数据从该地址到的行地址读出，以及开关信号输出部，用于根据WP和RP产生用于控制开关的开关信号。

6. 发明授权

US06980585B2 Receiving unit, receiving method and semiconductor device 有权
标题翻译：接收单元，接收方式和半导体器件
公开(公告)号：US06980585B2
公开(公告)日：2005-12-27
申请号：US10102814
申请日：2002-03-22
申请人： Yoshikazu Yamada , Shoji Taniguchi , Koichi Kuroiwa , Masami Kanasugi
发明人： Yoshikazu Yamada , Shoji Taniguchi , Koichi Kuroiwa , Masami Kanasugi
IPC分类号： H04B1/707 , H04B1/7085 , H04B1/7093 , H04B1/7117 , H04L1/69
CPC分类号： H04B1/7113 , H04B2201/7071
摘要： A receiving unit, receiving method, and semiconductor device that reduce the size of circuits in a receiving unit. A receiving section receives signals sent from a base station and transmitted through a plurality of paths. A path tracking section detects timing of each of the plurality of paths through which the signals received by the receiving section were transmitted. A demodulating section demodulates the received signals by performing a despreading process according to the timing of the plurality of paths detected by the path tracking section. A correlation value calculating section calculates a correlation value between the received signals and a spreading code. A destination selecting section provides output from the correlation value calculating section to the path tracking section in the case of performing a path tracking process by the path tracking section and provides output from the correlation value calculating section to the demodulating section in the case of demodulating the received signals by the demodulating section.
摘要翻译：一种减小接收单元中的电路尺寸的接收单元，接收方法和半导体器件。接收部分接收从基站发送并通过多个路径发送的信号。路径跟踪部分检测发送由接收部分接收的信号的多个路径中的每一个的定时。解调部通过根据由路径追踪部检测出的多个路径的定时进行解扩处理来解调接收信号。相关值计算部分计算接收信号和扩展码之间的相关值。目的地选择部分在路径跟踪部分执行路径跟踪处理的情况下，将相关值计算部分的输出提供给路径跟踪部分，并且在解调该解调部分的情况下将相关值计算部分的输出提供给解调部分由解调部分接收信号。

7. 发明授权

US06678315B1 Code phase setting method and apparatus 有权
标题翻译：码相位设定方法及装置
公开(公告)号：US06678315B1
公开(公告)日：2004-01-13
申请号：US09447234
申请日：1999-11-23
申请人： Mahiro Hikita , Shoji Taniguchi , Koichi Kuroiwa , Masami Kanasugi
发明人： Mahiro Hikita , Shoji Taniguchi , Koichi Kuroiwa , Masami Kanasugi
IPC分类号： H04L516
CPC分类号： H04J13/10 , H03K3/84 , H04J13/0022
摘要： A code phase setting method in a PN coder which includes a shift register is provided. According to the method, an initial value is set in the shift register and a direction is selected among two directions in which direction a value in the shift register is shifted. Then, a code phase is set by shifting the initial value in the direction a necessary number of times.
摘要翻译：提供了包括移位寄存器的PN编码器中的码相位设定方法。根据该方法，在移位寄存器中设置初始值，并且在移位寄存器中的值偏移方向的两个方向上选择方向。然后，通过将初始值沿着必要次数的方向移位来设置码相位。

8. 发明授权

US06639954B2 Mobile communication terminal and transmission-bit-rate detection method 失效
标题翻译：移动通信终端和传输比特率检测方法
公开(公告)号：US06639954B2
公开(公告)日：2003-10-28
申请号：US09318832
申请日：1999-05-26
申请人： Koichi Kuroiwa , Mahiro Hikita
发明人： Koichi Kuroiwa , Mahiro Hikita
IPC分类号： H04B726
CPC分类号： H04L1/0046 , H04L1/0054 , H04L1/006 , H04L1/0067 , H04L1/0071 , H04L25/0262
摘要： A mobile communication terminal which receives convolutionally encoded data that is convolutionally encoded information of a speech channel transmitted from a base station and detects a transmission bit rate selected at the base station by decoding the data. The mobile communication terminal comprises a rate estimation unit which estimates the transmission bit rate selected at the base station and outputs an estimated transmission bit rate, a decoding unit which decodes the convolutionally encoded data transmitted from the base station and outputs decoded data and predetermined types of results of decoding, a convolutional re-encoding unit which convolutionally re-encodes the decoded data and outputs re-encoded data, and a rate detection unit which detects whether the estimated transmission bit rate is correct or not based on the decoded data and the predetermined types of results of decoding.
摘要翻译：一种移动通信终端，其接收卷积编码的数据，所述卷积编码数据是从基站发送的语音信道的卷积编码信息，并且通过解码所述数据来检测在所述基站处选择的传输比特率。移动通信终端包括速率估计单元，其估计在基站处选择的传输比特率并输出估计的传输比特率;解码单元，对从基站发送的卷积编码数据进行解码，并输出解码数据和预定类型的解码结果，对解码数据进行卷积重新编码并输出再编码数据的卷积重编码单元，以及速率检测单元，其基于解码数据和预定的数据检测估计的传输比特率是否正确解码结果的类型。

9. 发明授权

US5309383A Floating-point division circuit 失效
标题翻译：浮点分割电路
公开(公告)号：US5309383A
公开(公告)日：1994-05-03
申请号：US946316
申请日：1992-11-09
申请人： Koichi Kuroiwa
发明人： Koichi Kuroiwa
IPC分类号： G06F7/537 , G06F7/483 , G06F7/499 , G06F7/52 , G06F7/535 , G06F7/38
CPC分类号： G06F7/535 , G06F7/5375 , G06F7/4873
摘要： A floating-point division circuit for performing division on floating-point data using a non-recovery type division method is disclosed. The floating-point division circuit includes a circuit portion for conducting a pre-division processing and pattern determination on a dividend and a divisor, an exponent operation portion, a mantissa division portion, and a quotient generating portion, further including either or both of an exception/non-operation detecting portion and a control portion. The exception/non-operation detecting portion generates a stop signal when detecting a non-operation pattern so as to stop a repetition of operations in the mantissa division portion. The control portion generates either a non-executional signal or a control signal so as to stop a latch operation during a period when no instruction for division is executed.
摘要翻译： PCT No.PCT / JP92 / 00296 Sec。 371日期：1992年11月9日 102（e）日期1992年11月9日PCT 1992年3月12日PCT公布。 WO92 / 16892 PCT出版物 1992年10月1日公开了一种使用非恢复型分割方法对浮点数据进行分割的浮点分割电路。浮点分割电路包括用于对除数和除数进行预分割处理和图案确定的电路部分，指数运算部分，尾数分割部分和商产生部分，还包括以下任一或两者：异常/非操作检测部分和控制部分。异常/非操作检测部分在检测非操作模式时产生停止信号，以停止尾数分割部分中的操作的重复。控制部分产生非执行信号或控制信号，以便在不执行分割指令的时段期间停止锁存操作。

10. 发明申请

US20080130393A1 Semiconductor memory and electronic device 有权
标题翻译：半导体存储器和电子器件
公开(公告)号：US20080130393A1
公开(公告)日：2008-06-05
申请号：US12000051
申请日：2007-12-07
申请人： Masami Kanasugi , Koichi Kuroiwa , Makoto Muranushi
发明人： Masami Kanasugi , Koichi Kuroiwa , Makoto Muranushi
IPC分类号： G11C7/00 , G11C8/00 , G11C5/14
CPC分类号： G11C8/08 , G11C5/14
摘要： A semiconductor memory that reduces the power consumption of a memory cell array without exercising control by a microprocessor. The semiconductor memory comprises a memory cell array, a switch for turning on/off power corresponding to row addresses of the memory cell array, an address control section for exercising sequence control on the basis of a write pointer (WP) generated at the time of a write signal being inputted for designating a row address to which data of a predetermined data stream is to be written and a read pointer (RP) generated at the time of a read signal being inputted for designating a row address from which the data is to be read out, and a switch signal output section for generating switch signals for controlling the switch on the basis of the WP and the RP.
摘要翻译：一种半导体存储器，其在不进行微处理器控制的情况下降低存储单元阵列的功耗。半导体存储器包括存储单元阵列，用于接通/关断与存储单元阵列的行地址相对应的功率的开关，用于基于在第一时钟产生的写指针（WP）进行序列控制的地址控制部分，输入写入信号，用于指定要写入预定数据流的数据的行地址和在输入读取信号时生成的读取指针（RP），用于指定数据从该地址到的行地址读出，以及开关信号输出部，用于根据WP和RP产生用于控制开关的开关信号。

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