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1. 发明授权

US07162563B2 Semiconductor integrated circuit having changeable bus width of external data signal 有权
标题翻译：半导体集成电路具有可变的外部数据信号的总线宽度
公开(公告)号：US07162563B2
公开(公告)日：2007-01-09
申请号：US10898339
申请日：2004-07-26
申请人： Satoshi Matsui , Seiji Suetake
发明人： Satoshi Matsui , Seiji Suetake
IPC分类号： G06F13/40 , G06F12/00
CPC分类号： G06F13/1678 , G06F13/4018
摘要： A data controlling unit activates a predetermined number of data terminals according to a mode signal and changes a bus width of external data signal. According to the mode signal, an address controlling unit selects a predetermined number of bits of an internal address signal outputted from a controller and outputs the selected bits as an external address signal. Specifically, the address controlling unit selects upper bits of the internal address signal when the bus width of the external data signal is increased according to the mode signal. Therefore, it is possible to prevent occurrence of an unused external address terminal, enabling the increase in accessible external memory capacity.
摘要翻译：数据控制单元根据模式信号激活预定数量的数据终端并改变外部数据信号的总线宽度。根据模式信号，地址控制单元选择从控制器输出的内部地址信号的预定数量的比特，并将所选择的比特输出为外部地址信号。具体地说，当根据模式信号增加外部数据信号的总线宽度时，地址控制单元选择内部地址信号的高位。因此，可以防止未使用的外部地址端子的发生，从而能够增加可访问的外部存储器容量。

2. 发明授权

US06880066B2 Central processing unit and system having a prefetch queue and a command cache to perform an efficient information reading operation 失效
标题翻译：中央处理单元和系统具有预取队列和命令高速缓存以执行有效的信息读取操作
公开(公告)号：US06880066B2
公开(公告)日：2005-04-12
申请号：US09421008
申请日：1999-10-20
申请人： Seiji Suetake
发明人： Seiji Suetake
IPC分类号： G06F9/38 , G06F12/08 , G06F15/76
CPC分类号： G06F9/3814 , G06F9/3802 , G06F12/0875
摘要： A central processing system can maintain an efficient information reading operation even when a program executed by a central processing unit contains many branch commands. A prefetch queue of the central processing unit reads and information expected to be processed next by the central processing unit from a main memory. The function of the prefetch queue is deactivated in accordance with a control signal provided from a prefetch queue control unit. A block transfer function of a cache memory is also deactivated when unnecessary information is read from the main memory in accordance with the block transfer function.
摘要翻译：即使当由中央处理单元执行的程序包含许多分支命令时，中央处理系统也可以保持有效的信息读取操作。中央处理单元的预取队列从主存储器读取和预期由中央处理单元接下来处理的信息。根据从预取队列控制单元提供的控制信号，预取队列的功能被去激活。根据块传送功能，当从主存储器读取不必要的信息时，缓存存储器的块传送功能也被去激活。

3. 发明授权

US08606974B2 Direct memory access controller 有权
标题翻译：直接内存访问控制器
公开(公告)号：US08606974B2
公开(公告)日：2013-12-10
申请号：US12730801
申请日：2010-03-24
申请人： Koji Takenouchi , Seiji Suetake
发明人： Koji Takenouchi , Seiji Suetake
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section.
摘要翻译：提供一种直接存储器访问控制器，其中存储控制设置信息的内部存储部分; 以及控制部，当传送请求信号不属于第一组时，将控制设置信息从外部存储部分加载到内部存储部分，并且不将控制设置信息从外部存储部分加载到内部存储部分，当控制设置信息转移请求信号属于第一组; 并且根据内部存储部分中的控制设置信息执行通过直接存储器访问的数据传送。

4. 发明授权

US07716390B2 Direct memory access controller 有权
标题翻译：直接内存访问控制器
公开(公告)号：US07716390B2
公开(公告)日：2010-05-11
申请号：US11707988
申请日：2007-02-20
申请人： Koji Takenouchi , Seiji Suetake
发明人： Koji Takenouchi , Seiji Suetake
IPC分类号： G06F13/28 , G06F3/00 , G06F5/00
CPC分类号： G06F13/28
摘要： A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section.
摘要翻译：提供一种直接存储器访问控制器，其中存储控制设置信息的内部存储部分; 以及控制部，当传送请求信号不属于第一组时，将控制设置信息从外部存储部分加载到内部存储部分，并且不将控制设置信息从外部存储部分加载到内部存储部分，当控制设置信息转移请求信号属于第一组; 并且根据内部存储部分中的控制设置信息执行通过直接存储器访问的数据传送。

5. 发明授权

US07634593B2 System and method for DMA transfer 有权
标题翻译： DMA传输的系统和方法
公开(公告)号：US07634593B2
公开(公告)日：2009-12-15
申请号：US11165244
申请日：2005-06-24
申请人： Seiji Suetake
发明人： Seiji Suetake
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F13/28
摘要： A system for DMA transfer includes a DMA controller, a bus connected to the DMA controller, a bus interface connected to the bus, and a plurality of registers coupled to the bus via the bus interface, wherein the bus interface is configured to allocate the plurality of registers doubly to nonconsecutive addresses and consecutive addresses to allow the DMA controller to access the plurality of registers through the consecutive addresses.
摘要翻译：用于DMA传输的系统包括DMA控制器，连接到DMA控制器的总线，连接到总线的总线接口以及经由总线接口耦合到总线的多个寄存器，其中总线接口被配置为分配多个的寄存器与非连续地址和连续地址相乘，以允许DMA控制器通过连续地址访问多个寄存器。

6. 发明申请

US20080040517A1 Direct memory access controller 有权
标题翻译：直接内存访问控制器
公开(公告)号：US20080040517A1
公开(公告)日：2008-02-14
申请号：US11707988
申请日：2007-02-20
申请人： Koji Takenouchi , Seiji Suetake
发明人： Koji Takenouchi , Seiji Suetake
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section.
摘要翻译：提供一种直接存储器访问控制器，其中存储控制设置信息的内部存储部分; 以及控制部，当传送请求信号不属于第一组时，将控制设置信息从外部存储部分加载到内部存储部分，并且不将控制设置信息从外部存储部分加载到内部存储部分，当控制设置信息转移请求信号属于第一组; 并且根据内部存储部分中的控制设置信息执行通过直接存储器访问的数据传送。

7. 发明申请

US20050083098A1 Clock shift circuit for gradual frequency change 有权
标题翻译：时钟移位电路，用于逐渐变频
公开(公告)号：US20050083098A1
公开(公告)日：2005-04-21
申请号：US10796005
申请日：2004-03-10
申请人： Satoshi Matsui , Yukihiro Ozawa , Seiji Suetake
发明人： Satoshi Matsui , Yukihiro Ozawa , Seiji Suetake
IPC分类号： G06F1/08 , H03K5/00 , H03K5/159
CPC分类号： G06F1/08
摘要： A circuit for changing clocks includes a clock generating circuit which generates an output clock signal by controlling a frequency of an original clock signal, and a control circuit which controls the clock generating circuit in response to an operation mode change signal indicative of a change from a first operation mode to a second operation mode of an external circuit operating based on the output clock signal, thereby changing the output clock signal from a first frequency corresponding to the first operation mode to an intervening frequency and then from the intervening frequency to a second frequency corresponding to the second operation mode, the intervening frequency having a frequency between the first frequency and the third frequency.
摘要翻译：用于改变时钟的电路包括：时钟发生电路，其通过控制原始时钟信号的频率来产生输出时钟信号;以及控制电路，其响应于指示从a的变化的操作模式改变信号控制时钟发生电路第一操作模式转换为基于输出时钟信号工作的外部电路的第二操作模式，从而将对应于第一操作模式的第一频率的输出时钟信号改变为中间频率，然后从中间频率改变为第二频率对应于第二操作模式，中间频率具有在第一频率和第三频率之间的频率。

8. 发明授权

US5822762A Information processing device with decision circuits and partitioned address areas 失效
标题翻译：具有决策电路和分区地址区的信息处理装置
公开(公告)号：US5822762A
公开(公告)日：1998-10-13
申请号：US533965
申请日：1995-09-26
申请人： Syuji Nishida , Seiji Suetake , Shunsuke Kamijo , Kenji Furuya
发明人： Syuji Nishida , Seiji Suetake , Shunsuke Kamijo , Kenji Furuya
IPC分类号： G06F12/08
CPC分类号： G06F12/0888
摘要： An information processing device includes a central processing unit, a cache memory unit and first and second decision circuits. The first decision circuit identifies one of partitioned address areas to be accessed before the central processing unit accesses the cache memory unit. The second decision circuit determines whether the above one of the partitioned address areas is a cachable area or a non-cachable area before address tag data is referred to in the cache memory unit.
摘要翻译：信息处理装置包括中央处理单元，高速缓冲存储器单元和第一和第二判定电路。在中央处理单元访问高速缓冲存储器单元之前，第一判定电路识别要访问的分割地址区域之一。第二判定电路在高速缓冲存储器单元中参考地址标签数据之前，确定上述一个分区地址区域是否为高速缓存区域或不可高速缓存区域。

9. 发明授权

US5822557A Pipelined data processing device having improved hardware control over an arithmetic operations unit 失效
标题翻译：具有对算术运算单元进行改进的硬件控制的流水线数据处理装置
公开(公告)号：US5822557A
公开(公告)日：1998-10-13
申请号：US586483
申请日：1996-01-16
申请人： Seiji Suetake , Koichi Hatta , Hideyuki Iino , Tatsuya Nagasawa
发明人： Seiji Suetake , Koichi Hatta , Hideyuki Iino , Tatsuya Nagasawa
IPC分类号： G01R31/3185 , G06F5/00 , G06F7/487 , G06F7/52 , G06F7/544 , G06F9/30 , G06F9/302 , G06F11/267 , G06F9/38
CPC分类号： G06F7/4876 , G06F11/2226 , G06F5/00 , G06F7/544 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G01R31/318536 , G06F2207/3884
摘要： An arithmetic operation unit for operating according to pipeline control and an instruction decoder for controlling the arithmetic operation unit by decoding an instruction, including a state retaining unit for retaining a state of the operation of the arithmetic operation unit, wherein the instruction decoder controls the execution of the arithmetic operation unit according to the information stored by the state retaining unit. A state is set when the decoder issues a signal for starting the arithmetic operation unit and the state is cleared when the decoder issues a signal for stopping the operation of the arithmetic operation unit. The arithmetic operation unit further comprises a unit for obtaining a maximum and a minimum value with a simple construction. A multiplier of the arithmetic operation unit comprises a unit for performing an addition of an exponential part of a multiplier and that of a multiplicand with a simple construction. The arithmetic operation unit further comprises a data packing and unpacking unit for packing and unpacking vector data. The data processing device is divided into several units and scan paths are divided into several paths corresponding to respective units.
摘要翻译：一种用于根据流水线控制操作的算术运算单元和一个用于通过解码指令来控制算术运算单元的指令译码器，该指令包括一个保持运算单元操作状态的状态保持单元，其中指令译码器控制执行根据由状态保持单元存储的信息来计算算术运算单元。当解码器发出用于启动算术运算单元的信号时，状态被设置，并且当解码器发出用于停止算术运算单元的运算的信号时，状态被清除。算术运算单元还包括用于以简单结构获得最大值和最小值的单元。算术运算单元的乘法器包括用于以简单结构执行乘法器的指数部分和被乘数的乘法器的相加的单元。算术运算单元还包括用于打包和解包矢量数据的数据打包和解包单元。数据处理装置被分成若干个单元，扫描路径被划分成与各个单元对应的若干路径。

10. 发明申请

US20100180053A1 DIRECT MEMORY ACCESS CONTROLLER 有权
标题翻译：直接存储器访问控制器
公开(公告)号：US20100180053A1
公开(公告)日：2010-07-15
申请号：US12730801
申请日：2010-03-24
申请人： Koji Takenouchi , Seiji Suetake
发明人： Koji Takenouchi , Seiji Suetake
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section.
摘要翻译：提供一种直接存储器访问控制器，其中存储控制设置信息的内部存储部分; 以及控制部，当传送请求信号不属于第一组时，将控制设置信息从外部存储部分加载到内部存储部分，并且不将控制设置信息从外部存储部分加载到内部存储部分，当控制设置信息转移请求信号属于第一组; 并且根据内部存储部分中的控制设置信息执行通过直接存储器访问的数据传送。

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