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1. 发明授权

US06775741B2 Cache system with limited number of tag memory accesses 有权
标题翻译：具有有限数量的标签存储器访问的缓存系统
公开(公告)号：US06775741B2
公开(公告)日：2004-08-10
申请号：US09768348
申请日：2001-01-25
申请人： Hidetaka Ebeshu , Hideaki Tomatsuri
发明人： Hidetaka Ebeshu , Hideaki Tomatsuri
IPC分类号： G06F1200
CPC分类号： G06F12/0882 , G06F2212/1028 , Y02D10/13
摘要： The present invention is a cache system comprising a data memory for storing data in an external memory, and a tag memory for storing address information for data held in the data memory and a valid data bit indicating whether data controlled by the address information is valid; wherein the address information in the tag memory commonly controls a plurality of data items with consecutive addresses; wherein reading from tag memory is prohibited in a case where an address to be accessed corresponds to data controlled by address information in tag memory that matches a preceding address to be accessed; and wherein tag memory is read and a cache hit determination is performed in a case where the address to be accessed corresponds to data controlled by address information in tag memory that does not match the preceding address to be accessed.
摘要翻译：本发明是一种缓存系统，包括用于在外部存储器中存储数据的数据存储器和用于存储数据存储器中保存的数据的地址信息的标签存储器和指示由地址信息控制的数据是否有效的有效数据位; 其中，所述标签存储器中的地址信息共同地控制具有连续地址的多个数据项; 在要访问的地址对应于标签存储器中与要访问的先前地址匹配的地址信息控制的数据的情况下，禁止从标签存储器读取; 并且其中标签存储器被读取，并且在要访问的地址对应于标签存储器中与要访问的前一个地址不匹配的地址信息控制的数据的情况下执行高速缓存命中确定。

2. 发明授权

US6167493A Semiconductor apparatus and read access method 失效
标题翻译：半导体装置及读取方式
公开(公告)号：US6167493A
公开(公告)日：2000-12-26
申请号：US863025
申请日：1997-05-23
申请人： Hidetaka Ebeshu , Hirotoshi Okada , Hideaki Tomatsuri
发明人： Hidetaka Ebeshu , Hirotoshi Okada , Hideaki Tomatsuri
IPC分类号： G06F12/06 , G06F13/16 , G06F13/18 , G06F15/78
CPC分类号： G06F13/18 , Y02D10/14
摘要： A CPU performs read access to a plurality of resources. A plurality of buffers connect the plurality of resources to the CPU, respectively. The CPU causes one of the plurality of buffers connected to one of the plurality of resources to be in an active state so that the CPU can perform read access to the one of the plurality of resources via the one of the plurality of buffers, the one of the plurality of resources being given priority.
摘要翻译： CPU执行对多个资源的读取访问。多个缓冲器分别将多个资源连接到CPU。 CPU使得与多个资源之一连接的多个缓冲器中的一个处于活动状态，使得CPU可以经由多个缓冲器中的一个来执行对多个资源之一的读取访问，多个资源的优先权。

3. 发明授权

US6078202A Semiconductor device having portions that operate at different frequencies, and method of designing the device 有权
标题翻译：具有以不同频率工作的部分的半导体器件，以及设计该器件的方法
公开(公告)号：US6078202A
公开(公告)日：2000-06-20
申请号：US134518
申请日：1998-08-14
申请人： Hideaki Tomatsuri , Hiroyuki Fujiyama , Noriaki Ono , Minoru Usui
发明人： Hideaki Tomatsuri , Hiroyuki Fujiyama , Noriaki Ono , Minoru Usui
IPC分类号： G06F1/06 , G06F1/12 , H03L7/00
CPC分类号： G06F1/12 , H03L7/00
摘要： Disclosed are a semiconductor device of which a block having a plurality of portions that operate based on a plurality of clocks can be designed and inspected easily, and a method of designing the semiconductor device. First and second clocks whose frequencies are mutually different are used to generate an enabling signal that is validated only during a short period including a transition edge of the second clock. The enabling signal and first clock are supplied to the second portion. The second portion synthesizes the enabling signal and first clock to substantially generate the second clock. Thus, the second portion is regarded as a portion that operates synchronously with the first clock.
摘要翻译：公开了一种半导体器件，其中可以容易地设计和检查具有基于多个时钟操作的多个部分的块，以及设计半导体器件的方法。其频率相互不同的第一和第二时钟用于产生仅在包括第二时钟的过渡沿的短周期期间被验证的使能信号。使能信号和第一时钟被提供给第二部分。第二部分合成使能信号和第一时钟以基本上产生第二时钟。因此，第二部分被认为是与第一时钟同步操作的部分。

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