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1. 发明授权

US09146835B2 Methods and systems with delayed execution of multiple processors 有权
标题翻译：延迟执行多个处理器的方法和系统
公开(公告)号：US09146835B2
公开(公告)日：2015-09-29
申请号：US13343809
申请日：2012-01-05
申请人： Mark D. Bellows , Mark S. Fredrickson , Scott D. Frei , Steven P. Jones , Chad B. McBride
发明人： Mark D. Bellows , Mark S. Fredrickson , Scott D. Frei , Steven P. Jones , Chad B. McBride
IPC分类号： G06F11/36 , G06F11/16
CPC分类号： G06F1/12 , G06F5/065 , G06F11/1695 , G06F11/366 , G06F2205/067
摘要： A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.
摘要翻译：第一先入先出（FIFO）存储器可以从包括第一处理器的第一处理器组接收第一处理器输入。第一处理器组被配置为基于包括一组输入信号，时钟信号和相应数据的第一处理器输入来执行程序代码。第一FIFO可以存储第一处理器输入，并且可以根据第一延迟将第一处理器输入输出到第二FIFO存储器和第二处理器。第二FIFO存储器可以存储第一处理器输入，并且可以根据第二延迟将第一处理器输入输出到第三处理器。第二处理器可以执行程序代码的至少第一部分，并且第三处理器可以响应于第一处理器输入来执行程序代码的至少第二部分。

2. 发明申请

US20130179720A1 MULTIPLE PROCESSOR DELAYED EXECUTION 有权
标题翻译：多处理器延迟执行
公开(公告)号：US20130179720A1
公开(公告)日：2013-07-11
申请号：US13343809
申请日：2012-01-05
申请人： Mark D. Bellows , Mark S. Fredrickson , Scott D. Frei , Steven P. Jones , Chad B. McBride
发明人： Mark D. Bellows , Mark S. Fredrickson , Scott D. Frei , Steven P. Jones , Chad B. McBride
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F5/065 , G06F11/1695 , G06F11/366 , G06F2205/067
摘要： A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.
摘要翻译：第一先入先出（FIFO）存储器可以从包括第一处理器的第一处理器组接收第一处理器输入。第一处理器组被配置为基于包括一组输入信号，时钟信号和相应数据的第一处理器输入来执行程序代码。第一FIFO可以存储第一处理器输入，并且可以根据第一延迟将第一处理器输入输出到第二FIFO存储器和第二处理器。第二FIFO存储器可以存储第一处理器输入，并且可以根据第二延迟将第一处理器输入输出到第三处理器。第二处理器可以执行程序代码的至少第一部分，并且第三处理器可以响应于第一处理器输入来执行程序代码的至少第二部分。

3. 发明申请

US20100180154A1 Built In Self-Test of Memory Stressor 审中-公开
标题翻译：内存自测测试
公开(公告)号：US20100180154A1
公开(公告)日：2010-07-15
申请号：US12352633
申请日：2009-01-13
申请人： Mark D. Bellows
发明人： Mark D. Bellows
IPC分类号： G06F11/00
CPC分类号： G11C29/20 , G11C5/04 , G11C2029/3602
摘要： A method and system for generating addresses in a memory card built in self-test (MCBIST) for testing memory devices. The method includes receiving a MCBIST command and determining an addressing mode of the MCBIST command. Sequential addresses are generated and modified in response to the addressing mode being a stress test mode. The modifying includes swapping bits in a sequential address with other bits in the sequential address to target selected portions of a memory. The modified sequential addresses are output to the memory to be utilized in a MCBIST stress test of the memory.
摘要翻译：一种用于生成内置自检（MCBIST）的存储卡中用于测试存储器件的地址的方法和系统。该方法包括接收MCBIST命令并确定MCBIST命令的寻址模式。响应于作为压力测试模式的寻址模式，生成和修改顺序地址。修改包括将顺序地址中的比特交换为顺序地址中的其他比特以定位存储器的所选部分。修改的顺序地址被输出到存储器，用于在存储器的MCBIST压力测试中使用。

4. 发明授权

US07757040B2 Memory command and address conversion between an XDR interface and a double data rate interface 失效
标题翻译： XDR接口和双数据速率接口之间的存储器命令和地址转换
公开(公告)号：US07757040B2
公开(公告)日：2010-07-13
申请号：US11680751
申请日：2007-03-01
申请人： Mark D. Bellows , John D. Irish , David A. Norgaard , Tolga Ozguner
发明人： Mark D. Bellows , John D. Irish , David A. Norgaard , Tolga Ozguner
IPC分类号： G06F12/00
CPC分类号： G06F13/1694 , G06F12/0292
摘要： A command translation method, apparatus and system are provided for interfacing a processor and a memory. The processor initiates a memory system command in an extreme data rate (XDR) command format which is automatically converted by the command translation method, apparatus and system into a memory system command in a double data rate (DDR) format for forwarding to the memory. Associated with converting the memory system command to the DDR command format is controlling timing of one or more signals presented to the memory interface, the one or more signals being associated with processing the memory system command in the DDR command format. The processor has associated therewith an XDR memory interface controller which adjusts one or more timing parameters of the memory system command in the XDR command format so that DDR timing requirements for the memory system command in the DDR command format are met.
摘要翻译：提供了一种命令翻译方法，装置和系统，用于接口处理器和存储器。处理器以极端数据速率（XDR）命令格式发起存储器系统命令，该命令格式由命令转换方法，装置和系统自动转换成双数据速率（DDR）格式的存储器系统命令，用于转发到存储器。与将存储器系统命令转换为DDR命令格式相关联的是将呈现给存储器接口的一个或多个信号的定时控制，该一个或多个信号与DDR命令格式的处理存储器系统命令相关联。处理器具有与其相关联的XDR存储器接口控制器，其以XDR命令格式调整存储器系统命令的一个或多个定时参数，使得满足DDR命令格式的存储器系统命令的DDR定时要求。

5. 发明授权

US07669028B2 Optimizing data bandwidth across a variable asynchronous clock domain 有权
标题翻译：优化跨可变异步时钟域的数据带宽
公开(公告)号：US07669028B2
公开(公告)日：2010-02-23
申请号：US11348884
申请日：2006-02-07
申请人： Mark D. Bellows , Brian M. McKevett , Tolga Ozguner
发明人： Mark D. Bellows , Brian M. McKevett , Tolga Ozguner
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/1689
摘要： Embodiments of the present invention optimize data bandwidth across an asynchronous buffer in a system with a variable clock domain. A move signal may be asserted to transfer data associated with a command into the asynchronous buffer. After the data has been moved into the buffer, an acknowledge signal may indicate that the transfer is complete. A launch signal may transfer the data in the asynchronous buffer to memory. Embodiments of the present invention allow the processing of a next command to begin at the earliest possible time while data associated with a previous command is being transferred into and out of the buffer, thereby increasing throughput and improving performance.
摘要翻译：本发明的实施例通过具有可变时钟域的系统中的异步缓冲器来优化数据带宽。可以断言移动信号将与命令相关联的数据传送到异步缓冲器。数据移入缓冲区后，确认信号可能表示传输完成。发射信号可以将异步缓冲器中的数据传输到存储器。本发明的实施例允许下一个命令的处理在尽可能早的时间开始，而与先前命令相关联的数据正被传入和传出缓冲器，从而提高吞吐量并提高性能。

6. 发明申请

US20080229007A1 Enhancements to an XDR Memory Controller to Allow for Conversion to DDR2 审中-公开
标题翻译：增强XDR内存控制器以允许转换为DDR2
公开(公告)号：US20080229007A1
公开(公告)日：2008-09-18
申请号：US11686629
申请日：2007-03-15
申请人： Mark D. Bellows , Paul A. Ganfield , Kent H. Haselhorst , Ryan A. Heckendorf
发明人： Mark D. Bellows , Paul A. Ganfield , Kent H. Haselhorst , Ryan A. Heckendorf
IPC分类号： G06F12/00
CPC分类号： G06F13/1694
摘要： A memory control apparatus includes a data stream format converter and a physical layer converter. The data stream format converter is configured to convert an incoming data stream that has a data stream format corresponding to a first memory type into a format-converted data stream that has a data stream format corresponding to a second memory type. The second memory type is different from the first memory type. The physical layer converter is configured to convert the format-converted data stream into a physical-layer-converted data stream that has at least one physical parameter corresponding to the second memory type. The format-converted data stream has at least one physical parameter corresponding to the first memory type.
摘要翻译：存储控制装置包括数据流格式转换器和物理层转换器。数据流格式转换器被配置为将具有与第一存储器类型相对应的数据流格式的输入数据流转换成具有对应于第二存储器类型的数据流格式的格式转换的数据流。第二种存储器类型与第一种存储器类型不同。物理层转换器被配置为将格式转换的数据流转换成具有对应于第二存储器类型的至少一个物理参数的物理层转换的数据流。格式转换的数据流具有对应于第一存储器类型的至少一个物理参数。

7. 发明申请

US20080183925A1 Memory Command and Address Conversion Between an XDR Interface and a Double Data Rate Interface 失效
标题翻译： XDR接口和双数据速率接口之间的存储器命令和地址转换
公开(公告)号：US20080183925A1
公开(公告)日：2008-07-31
申请号：US11680751
申请日：2007-03-01
申请人： Mark D. Bellows , John D. Irish , David A. Norgaard , Tolga Ozguner
发明人： Mark D. Bellows , John D. Irish , David A. Norgaard , Tolga Ozguner
IPC分类号： G06F13/42
CPC分类号： G06F13/1694 , G06F12/0292
摘要： A command translation method, apparatus and system are provided for interfacing a processor and a memory. The processor initiates a memory system command in an extreme data rate (XDR) command format which is automatically converted by the command translation method, apparatus and system into a memory system command in a double data rate (DDR) format for forwarding to the memory. Associated with converting the memory system command to the DDR command format is controlling timing of one or more signals presented to the memory interface, the one or more signals being associated with processing the memory system command in the DDR command format. The processor has associated therewith an XDR memory interface controller which adjusts one or more timing parameters of the memory system command in the XDR command format so that DDR timing requirements for the memory system command in the DDR command format are met.
摘要翻译：提供了一种命令翻译方法，装置和系统，用于接口处理器和存储器。处理器以极端数据速率（XDR）命令格式发起存储器系统命令，该命令格式由命令转换方法，装置和系统自动转换成双数据速率（DDR）格式的存储器系统命令，用于转发到存储器。与将存储器系统命令转换为DDR命令格式相关联的是将呈现给存储器接口的一个或多个信号的定时控制，该一个或多个信号与DDR命令格式的处理存储器系统命令相关联。处理器具有与其相关联的XDR存储器接口控制器，其以XDR命令格式调整存储器系统命令的一个或多个定时参数，使得满足DDR命令格式的存储器系统命令的DDR定时要求。

8. 发明授权

US07380083B2 Memory controller capable of locating an open command cycle to issue a precharge packet 有权
标题翻译：存储器控制器能够定位打开的命令周期以发出预充电分组
公开(公告)号：US07380083B2
公开(公告)日：2008-05-27
申请号：US11204411
申请日：2005-08-16
申请人： Mark D. Bellows , Ryan A. Heckendorf
发明人： Mark D. Bellows , Ryan A. Heckendorf
IPC分类号： G06F12/00
CPC分类号： G06F13/1626
摘要： A memory controller capable of locating an open command cycle for the purpose of issuing a precharge packet to extreme data rate (XDR) dynamic random access memory (DRAM) devices is disclosed. In response to a receipt of two request packets concurrently, a determination is made as to whether one of the request packets includes a non-precharge command and the other one of the request packets includes a precharge command. If one of the request packets includes a non-precharge command and the other one of the request packets includes a precharge command, the request packet having a non-precharge command proceeds. In addition, the precharge command is deferred and its dynamic offset is adjusted accordingly.
摘要翻译：公开了一种能够定位用于将预充电分组发送到极端数据速率（XDR）动态随机存取存储器（DRAM）设备）的开放命令周期的存储器控制器。响应于同时接收到两个请求分组，确定请求分组中的一个是否包括非预充电命令，并且另一个请求分组包括预充电命令。如果一个请求分组包括非预充电命令，另一个请求分组包括预充电命令，则具有非预充电命令的请求分组进行。此外，预充电命令被延迟，并且相应地调整其动态偏移。

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