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1. 发明申请

US20120272009A1 METHODS AND APPARATUS FOR HANDLING A CACHE MISS 有权
标题翻译：处理缓存错误的方法和设备
公开(公告)号：US20120272009A1
公开(公告)日：2012-10-25
申请号：US13540684
申请日：2012-07-03
申请人： John D. Irish , Chad B. McBride , Andrew H. Wottreng
发明人： John D. Irish , Chad B. McBride , Andrew H. Wottreng
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/0862 , G06F12/1027 , G06F12/127 , G06F2212/654
摘要： In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了第一种方法。第一种方法包括以下步骤：（1）提供具有多个高速缓存条目的高速缓存，每个条目适于存储数据，其中高速缓存适于在第一操作模式中由硬件和软件进行访问; （2）确定在所述多个高速缓存条目之一中不存在期望数据; （3）基于当前操作模式和与所述多个高速缓存条目相关联的提示锁定位的值来确定状态; 以及（4）基于所述状态来确定所述高速缓存条目中的至少一个的可用性，其中高速缓存条目的可用性指示可以替换存储在所述高速缓存条目中的数据。提供了许多其他方面。

2. 发明申请

US20080059672A1 Methods and Apparatus for Scheduling Prioritized Commands on a Bus 审中-公开
标题翻译：在总线上调度优先级命令的方法和装置
公开(公告)号：US20080059672A1
公开(公告)日：2008-03-06
申请号：US11468377
申请日：2006-08-30
申请人： John D. Irish , Chad B. McBride , David A. Norgaard , Dorothy M. Thelen
发明人： John D. Irish , Chad B. McBride , David A. Norgaard , Dorothy M. Thelen
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： In a first aspect, a first method of scheduling a command to be issued on a bus is provided. The first method includes the steps of (1) associating an address and priority with each of a plurality of commands to be issued on the bus, wherein the priority associated with each command is based on the address associated with the command; (2) updating the priority associated with each command after a predetermined time period; and (3) from the plurality of commands, selecting a command to be issued on the bus based on the address and updated priority associated with the command to be issued. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种调度在总线上发出的命令的方法。第一种方法包括以下步骤：（1）将地址和优先级与要在总线上发出的多个命令中的每一个相关联，其中与每个命令相关联的优先级基于与该命令相关联的地址; （2）在预定时间段之后更新与每个命令相关联的优先级; 和（3）根据多个命令，基于与要发出的命令相关联的地址和更新的优先级来选择要在总线上发出的命令。提供了许多其他方面。

3. 发明申请

US20070283121A1 Method and Apparatus for Handling Concurrent Address Translation Cache Misses and Hits Under Those Misses While Maintaining Command Order 失效
标题翻译：在维护命令顺序的同时处理并发地址转换缓存缺失和命中的方法和装置
公开(公告)号：US20070283121A1
公开(公告)日：2007-12-06
申请号：US11420884
申请日：2006-05-30
申请人： John D. Irish , Chad B. McBride , Ibrahim A. Ouda , Andrew H. Wottreng
发明人： John D. Irish , Chad B. McBride , Ibrahim A. Ouda , Andrew H. Wottreng
IPC分类号： G06F12/00
CPC分类号： G06F12/1027
摘要： A method and apparatus handles concurrent address translation cache misses and hits under those misses while maintaining command order based upon virtual channel. Commands are stored in a command processing unit that maintains ordering of the commands. A command buffer index is assigned to each address being sent from the command processing unit to an address translation unit. When an address translation cache miss occurs, a memory fetch request is sent. The CBI is passed back to the command processing unit with a signal to indicate that the fetch request has completed. The command processing unit uses the CBI to locate the command and address to be reissued to the address translation unit.
摘要翻译：一种方法和装置处理并发的地址转换高速缓存未命中和命中命中，同时维持基于虚拟通道的命令顺序。命令存储在维护命令排序的命令处理单元中。将命令缓冲器索引分配给从命令处理单元发送到地址转换单元的每个地址。当发生地址转换高速缓存未命中时，发送存储器提取请求。 CBI被传回给具有信号的命令处理单元，以指示提取请求已经完成。命令处理单元使用CBI将要重新发布的命令和地址定位到地址转换单元。

4. 发明授权

US07716423B2 Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes 有权
标题翻译：用于虚拟锁定的伪LRU算法在软件和硬件地址转换缓存未命中处理模式下
公开(公告)号：US07716423B2
公开(公告)日：2010-05-11
申请号：US11348971
申请日：2006-02-07
申请人： John D. Irish , Chad B. McBride , Andrew H. Wottreng
发明人： John D. Irish , Chad B. McBride , Andrew H. Wottreng
IPC分类号： G06F12/00 , G06F13/28 , G06F13/00
CPC分类号： G06F12/126 , G06F12/123 , G06F2212/6042
摘要： The present invention provides an improved way to calculate a replacement way within a processor cache that is effective with different combinations of hardware address translation cache miss handling, software address translation cache miss handling, and hint lock bits. For some embodiments, LRU bits used to select an entry for replacement are updated only if software address translation cache miss handling is disabled. Further, for some embodiments, LRU bits may be modified to change the way a binary tree structure is traversed to avoid selecting a hint locked entry for replacement.
摘要翻译：本发明提供了一种用于计算处理器高速缓存中的替换方式的改进方法，该替换方式对于硬件地址转换高速缓存未命中处理，软件地址转换高速缓存未命中处理和提示锁定位的不同组合是有效的。对于一些实施例，仅当禁用软件地址转换高速缓存未命中处理时，才更新用于选择用于替换的条目的LRU位。此外，对于一些实施例，可以修改LRU比特以改变遍历二叉树结构的方式，以避免选择用于替换的提示锁定条目。

5. 发明申请

US20090187695A1 HANDLING CONCURRENT ADDRESS TRANSLATION CACHE MISSES AND HITS UNDER THOSE MISSES WHILE MAINTAINING COMMAND ORDER 审中-公开
标题翻译：处理相关地址转换缓存错误和维护命令命令之前的错误
公开(公告)号：US20090187695A1
公开(公告)日：2009-07-23
申请号：US12351900
申请日：2009-01-12
申请人： John D. Irish , Chad B. McBride , Ibrahim A. Ouda , Andrew H. Wottreng
发明人： John D. Irish , Chad B. McBride , Ibrahim A. Ouda , Andrew H. Wottreng
IPC分类号： G06F12/08 , G06F12/00 , G06F12/10
CPC分类号： G06F12/1027
摘要： Apparatus handles concurrent address translation cache misses and hits under those misses while maintaining command order based upon virtual channel. Commands are stored in a command processing unit that maintains ordering of the commands. A command buffer index is assigned to each address being sent from the command processing unit to an address translation unit. When an address translation cache miss occurs, a memory fetch request is sent. The CBI is passed back to the command processing unit with a signal to indicate that the fetch request has completed. The command processing unit uses the CBI to locate the command and address to be reissued to the address translation unit.
摘要翻译：设备处理并发地址转换高速缓存未命中和命中在这些未命中，同时维持基于虚拟通道的命令顺序。命令存储在维护命令排序的命令处理单元中。将命令缓冲器索引分配给从命令处理单元发送到地址转换单元的每个地址。当发生地址转换高速缓存未命中时，发送存储器提取请求。 CBI被传回给具有信号的命令处理单元，以指示提取请求已经完成。命令处理单元使用CBI将要重新发布的命令和地址定位到地址转换单元。

6. 发明授权

US08589630B2 Methods and apparatus for handling a cache miss 有权
标题翻译：用于处理高速缓存未命中的方法和装置
公开(公告)号：US08589630B2
公开(公告)日：2013-11-19
申请号：US13540684
申请日：2012-07-03
申请人： John D. Irish , Chad B. McBride , Andrew H. Wottreng
发明人： John D. Irish , Chad B. McBride , Andrew H. Wottreng
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/126 , G06F12/0862 , G06F12/1027 , G06F12/127 , G06F2212/654
摘要： In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了第一种方法。第一种方法包括以下步骤：（1）提供具有多个高速缓存条目的高速缓存，每个条目适于存储数据，其中高速缓存适于在第一操作模式中由硬件和软件进行访问; （2）确定在所述多个高速缓存条目之一中不存在期望数据; （3）基于当前操作模式和与所述多个高速缓存条目相关联的提示锁定位的值来确定状态; 以及（4）基于所述状态来确定所述高速缓存条目中的至少一个的可用性，其中高速缓存条目的可用性指示可以替换存储在所述高速缓存条目中的数据。提供了许多其他方面。

7. 发明授权

US08327075B2 Methods and apparatus for handling a cache miss 失效
标题翻译：用于处理高速缓存未命中的方法和装置
公开(公告)号：US08327075B2
公开(公告)日：2012-12-04
申请号：US11297312
申请日：2005-12-08
申请人： John D. Irish , Chad B. McBride , Andrew H. Wottreng
发明人： John D. Irish , Chad B. McBride , Andrew H. Wottreng
IPC分类号： G06F12/12
CPC分类号： G06F12/126 , G06F12/0862 , G06F12/1027 , G06F12/127 , G06F2212/654
摘要： In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了第一种方法。第一种方法包括以下步骤：（1）提供具有多个高速缓存条目的高速缓存，每个条目适于存储数据，其中高速缓存适于在第一操作模式中由硬件和软件进行访问; （2）确定在所述多个高速缓存条目之一中不存在期望数据; （3）基于当前操作模式和与所述多个高速缓存条目相关联的提示锁定位的值来确定状态; 以及（4）基于所述状态来确定所述高速缓存条目中的至少一个的可用性，其中高速缓存条目的可用性指示可以替换存储在所述高速缓存条目中的数据。提供了许多其他方面。

8. 发明授权

US08127082B2 Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations 失效
标题翻译：允许不间断地址转换同时执行地址转换高速缓存无效和其它高速缓存操作的方法和装置
公开(公告)号：US08127082B2
公开(公告)日：2012-02-28
申请号：US11344900
申请日：2006-02-01
申请人： Chad B. McBride , Andrew H. Wottreng , John D. Irish
发明人： Chad B. McBride , Andrew H. Wottreng , John D. Irish
IPC分类号： G06F12/00
CPC分类号： G06F12/1027
摘要： A method and apparatus for allowing multiple devices access to an address translation cache while cache maintenance operations are occurring at the same time. By interleaving the commands requiring address translation with maintenance operations that may normally take many cycles, address translation requests may have faster access to the address translation cache than if maintenance operations were allowed to stall commands requiring address translations until the maintenance operation was completed.
摘要翻译：一种用于允许多个设备访问地址转换高速缓存并且同时进行高速缓存维护操作的方法和装置。通过将需要地址转换的命令与可能通常需要许多周期的维护操作交错，与维护操作被允许停止需要地址转换的命令直到维护操作完成之前，地址转换请求可能具有对地址转换缓存的更快访问。

9. 发明授权

US07539840B2 Handling concurrent address translation cache misses and hits under those misses while maintaining command order 失效
标题翻译：在维护命令顺序的同时，处理并发地址转换高速缓存未命中和命中
公开(公告)号：US07539840B2
公开(公告)日：2009-05-26
申请号：US11420884
申请日：2006-05-30
申请人： John D. Irish , Chad B. McBride , Ibrahim A. Ouda , Andrew H. Wottreng
发明人： John D. Irish , Chad B. McBride , Ibrahim A. Ouda , Andrew H. Wottreng
IPC分类号： G06F12/00
CPC分类号： G06F12/1027
摘要： A method handles concurrent address translation cache misses and hits under those misses while maintaining command order based upon virtual channel. Commands are stored in a command processing unit that maintains ordering of the commands. A command buffer index is assigned to each address being sent from the command processing unit to an address translation unit. When an address translation cache miss occurs, a memory fetch request is sent. The CBI is passed back to the command processing unit with a signal to indicate that the fetch request has completed. The command processing unit uses the CBI to locate the command and address to be reissued to the address translation unit.
摘要翻译：一种方法处理并发地址转换高速缓存未命中并在这些未命中的命中，同时维持基于虚拟通道的命令顺序。命令存储在维护命令排序的命令处理单元中。将命令缓冲器索引分配给从命令处理单元发送到地址转换单元的每个地址。当发生地址转换高速缓存未命中时，发送存储器提取请求。 CBI被传回给具有信号的命令处理单元，以指示提取请求已经完成。命令处理单元使用CBI将要重新发布的命令和地址定位到地址转换单元。

10. 发明申请

US20080189501A1 Methods and Apparatus for Issuing Commands on a Bus 审中-公开
标题翻译：在公共汽车上发出命令的方法和装置
公开(公告)号：US20080189501A1
公开(公告)日：2008-08-07
申请号：US11671117
申请日：2007-02-05
申请人： John D. Irish , Chad B. McBride
发明人： John D. Irish , Chad B. McBride
IPC分类号： G06F12/00
CPC分类号： G06F13/1631
摘要： In a first aspect, a first method of issuing a command on a bus of a system is provided. The first method includes the steps of (1) receiving a first functional memory command in the system; (2) receiving a command to force the system to execute functional memory commands in order; (3) receiving a second functional memory command in the system; and (4) employing a dependency matrix to indicate the second functional memory command requires access to a same address as the first functional memory command whether or not the second functional memory command actually has an ordering dependency on the first functional memory command. The dependency matrix is adapted to store data indicating whether a functional memory command received by the system has an ordering dependency on one or more functional memory commands previously received by the system. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种在系统总线上发出命令的方法。第一种方法包括以下步骤：（1）在系统中接收第一功能存储器命令; （2）接收强制系统依次执行功能存储器命令的命令; （3）在系统中接收第二功能存储器命令; 和（4）使用依赖矩阵来指示第二功能存储器命令需要访问与第一功能存储器命令相同的地址，无论第二功能存储器命令是否实际上具有对第一功能存储器命令的排序依赖性。依赖矩阵适于存储指示系统接收的功能存储器命令是否具有与先前由系统接收的一个或多个功能存储器命令的排序依赖关系的数据。提供了许多其他方面。

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