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1. 发明授权

US06773990B1 Method for reducing short channel effects in memory cells and related structure 有权
标题翻译：减少存储单元短路效应的方法及相关结构
公开(公告)号：US06773990B1
公开(公告)日：2004-08-10
申请号：US10429150
申请日：2003-05-03
申请人： Richard Fastow , Yue-Song He , Kazuhiro Mizutani , Timothy Thurgate
发明人： Richard Fastow , Yue-Song He , Kazuhiro Mizutani , Timothy Thurgate
IPC分类号： H10L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region. The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region.
摘要翻译：根据一个示例性实施例，一种用于制造浮动栅极存储器阵列的方法包括从位于衬底中的隔离区域去除介电材料以暴露沟槽的步骤，其中沟槽位于第一源区域和第二源极之间区域，其中沟槽限定衬底中的侧壁。该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入N型掺杂剂，其中N型掺杂剂形成N +型区域。该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入P型掺杂剂，其中P型掺杂剂形成P型区域，并且其中P型区域位于N +型下方地区。

2. 发明授权

US06963106B1 Memory array with memory cells having reduced short channel effects 有权
标题翻译：具有存储单元的存储器阵列具有减少的短通道效应
公开(公告)号：US06963106B1
公开(公告)日：2005-11-08
申请号：US10839626
申请日：2004-05-04
申请人： Richard Fastow , Yue-Song He , Kazuhiro Mizutani , Timothy Thurgate
发明人： Richard Fastow , Yue-Song He , Kazuhiro Mizutani , Timothy Thurgate
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region. The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region.
摘要翻译：根据一个示例性实施例，一种用于制造浮动栅极存储器阵列的方法包括从位于衬底中的隔离区域去除介电材料以暴露沟槽的步骤，其中沟槽位于第一源区域和第二源极之间区域，其中沟槽限定衬底中的侧壁。该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入N型掺杂剂，其中N型掺杂剂形成N +型区域。该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入P型掺杂剂，其中P型掺杂剂形成P型区域，并且其中P型区域位于N +型下方地区。

3. 发明授权

US07301193B2 Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元中低Vss电阻和减少DIBL的结构和方法
公开(公告)号：US07301193B2
公开(公告)日：2007-11-27
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

4. 发明申请

US20050164450A1 Structure and method for low Vss resistance and reduced dibl in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元的低Vss电阻和二极管的结构和方法
公开(公告)号：US20050164450A1
公开(公告)日：2005-07-28
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L21/28 , H01L21/336 , H01L21/74 , H01L29/417 , H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

5. 发明授权

US06524914B1 Source side boron implanting and diffusing device architecture for deep sub 0.18 micron flash memory 有权
标题翻译：源极硼注入和扩散器件架构，用于深亚0.18微米闪存
公开(公告)号：US06524914B1
公开(公告)日：2003-02-25
申请号：US09699972
申请日：2000-10-30
申请人： Yue-song He , Sameer Haddad , Timothy Thurgate , Chi Chang
发明人： Yue-song He , Sameer Haddad , Timothy Thurgate , Chi Chang
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , H01L29/66833
摘要： One aspect of the present invention relates to a method of making a flash memory cell involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; cleaning the substrate; and implanting a medium dosage drain implant of a second type to form a source region and a drain region in the substrate adjacent the flash memory cell.
摘要翻译：本发明的一个方面涉及一种制造闪存单元的方法，所述闪存单元包括以下步骤：提供其上具有闪存单元的基板; 在衬底上形成自对准源掩模，所述自对准源掩模具有对应于源极线的开口; 通过对应于源极线的自对准源掩模中的开口将衬底中的第一类型源掺杂剂注入到衬底中; 从衬底去除自对准源掩模; 清洗基材; 以及植入第二类型的介质剂量漏极注入以在所述衬底中邻近所述闪存单元形成源极区域和漏极区域。

6. 发明授权

US06653189B1 Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory 有权
标题翻译：源极硼注入和漏极侧MDD植入物用于深亚0.18微米闪存
公开(公告)号：US06653189B1
公开(公告)日：2003-11-25
申请号：US09699711
申请日：2000-10-30
申请人： Sameer Haddad , Yue-song He , Timothy Thurgate , Chi Chang , Mark W. Randolph , Ngaching Wong
发明人： Sameer Haddad , Yue-song He , Timothy Thurgate , Chi Chang , Mark W. Randolph , Ngaching Wong
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L29/66833
摘要： One aspect of the present invention relates to a method of making a flash memory cell, involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; forming a MDD mask over the substrate, the MDD mask covering the source lines and having openings corresponding to drain lines; and implanting a medium dosage drain implant of a second type to form a drain region in the substrate adjacent the flash memory cell.
摘要翻译：本发明的一个方面涉及一种制造闪存单元的方法，包括以下步骤：在其上提供闪存单元; 在衬底上形成自对准源掩模，所述自对准源掩模具有对应于源极线的开口; 通过对应于源极线的自对准源掩模中的开口将衬底中的第一类型源掺杂剂注入到衬底中; 从衬底去除自对准源掩模; 在衬底上形成MDD掩模，MDD掩模覆盖源极线并具有对应于漏极线的开口; 以及植入第二类型的介质剂量漏极注入，以在与所述闪存单元相邻的所述衬底中形成漏极区域。

7. 发明授权

US07009271B1 Memory device with an alternating Vss interconnection 有权
标题翻译：具有交替Vss互连的存储器件
公开(公告)号：US07009271B1
公开(公告)日：2006-03-07
申请号：US10823972
申请日：2004-04-13
申请人： Timothy Thurgate , Richard Fastow
发明人： Timothy Thurgate , Richard Fastow
IPC分类号： H01L29/00
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A semiconductor memory device provides non-volatile memory with a memory array having an alternating Vss interconnection. Using the alternating Vss interconnection, a low implant dosage is added to a region proximate to the lower areas of an STI region, such as beneath the STI region, to ameliorate the problem of low Vss conductivity by providing an adequate number of multiple current paths over several Vss lines. However, non-adjacent STI regions, rather than adjacent STI region, receive the implant. Alternating Vss lines are interconnected by thus implanting under every other STI region. This alternating Vss interconnection imparts an adequately high Vss conductivity, yet without diffusion areas merging to isolate the associated memory device or contaminating the drains and maintains scalability.
摘要翻译：半导体存储器件提供具有交替Vss互连的存储器阵列的非易失性存储器。使用交替的Vss互连，将低植入剂量添加到靠近STI区域的较低区域（例如STI区域下方）的区域，以通过提供足够数量的多个电流路径来改善低Vss电导率的问题几条Vss线。然而，非相邻的STI区域而不是相邻的STI区域接收植入物。交替的Vss线通过在每个其它STI区域下植入而相互连接。这种交替的Vss互连赋予了足够高的Vss电导率，但没有扩散区域合并以隔离相关联的存储器件或污染漏极并保持可扩展性。

8. 发明申请

US20050077567A1 Memory cell array with staggered local inter-connect structure 失效
标题翻译：具有交错局部互连结构的存储单元阵列
公开(公告)号：US20050077567A1
公开(公告)日：2005-04-14
申请号：US10685044
申请日：2003-10-14
申请人： Mark Randolph , Sameer Haddad , Timothy Thurgate , Richard Fastow
发明人： Mark Randolph , Sameer Haddad , Timothy Thurgate , Richard Fastow
IPC分类号： G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521
摘要： A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.
摘要翻译：存储单元阵列包括在半导体衬底上制造的存储器单元的二维阵列。存储单元布置成多行和多列。每列存储单元包括多个交替沟道区和源极/漏极区。导电互连位于每个源极/漏极区域上方并且仅耦合到另一个源极/漏极区域。另一个源/漏区位于与该列相邻的第二列中。导电互连被定位成使得每隔一个导电布线连接到列的右侧的相邻列，并且每隔一个导电布线连接到列的左侧的相邻列。多个源极/漏极控制线在相邻列的存储器单元之间延伸，并且电耦合到在相邻列之间耦合的每个导电互连。

9. 发明授权

US06911704B2 Memory cell array with staggered local inter-connect structure 失效
公开(公告)号：US06911704B2
公开(公告)日：2005-06-28
申请号：US10685044
申请日：2003-10-14
申请人： Mark W. Randolph , Sameer S. Haddad , Timothy Thurgate , Richard Fastow
发明人： Mark W. Randolph , Sameer S. Haddad , Timothy Thurgate , Richard Fastow
IPC分类号： G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L27/082
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521
摘要： A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.

10. 发明授权

US08531878B2 Techniques for providing a semiconductor memory device 有权
标题翻译：提供半导体存储器件的技术
公开(公告)号：US08531878B2
公开(公告)日：2013-09-10
申请号：US13109821
申请日：2011-05-17
申请人： Srinivasa Rao Banna , Michael A. Van Buskirk , Timothy Thurgate
发明人： Srinivasa Rao Banna , Michael A. Van Buskirk , Timothy Thurgate
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0441 , G11C16/0475 , G11C16/0483 , H01L27/11556 , H01L29/66825 , H01L29/7889
摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.
摘要翻译：公开了一种用于提供半导体存储器件的技术。在一个特定实施例中，这些技术可被实现为半导体存储器件，其包括布置成行和列阵列的多个存储器单元，每个存储器单元。每个存储单元可以包括耦合到源极线的第一区域，耦合到位线的第二区域和经由栅极区域电容耦合到至少一个字线并且被布置在第一区域和第二区域之间的体区域区域，其中所述主体区域可以包括多个浮动体区域和电容耦合到所述至少一个字线的多个浮动栅极区域。

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