专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06911704B2 Memory cell array with staggered local inter-connect structure 失效
公开(公告)号：US06911704B2
公开(公告)日：2005-06-28
申请号：US10685044
申请日：2003-10-14
申请人： Mark W. Randolph , Sameer S. Haddad , Timothy Thurgate , Richard Fastow
发明人： Mark W. Randolph , Sameer S. Haddad , Timothy Thurgate , Richard Fastow
IPC分类号： G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L27/082
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521
摘要： A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.

2. 发明授权

US06252803B1 Automatic program disturb with intelligent soft programming for flash cells 有权
标题翻译：自动程序干扰与闪存单元的智能软编程
公开(公告)号：US06252803B1
公开(公告)日：2001-06-26
申请号：US09692881
申请日：2000-10-23
申请人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland , Chi Chang
发明人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland , Chi Chang
IPC分类号： G11C1616
CPC分类号： G11C16/16
摘要： A method of erasing a flash electrically-erasable programmable read-only memory (EEPROM) device is provided which includes a plurality of memory cells. An erase pulse is applied to the plurality of memory cells. The plurality of memory cells is overerase verified and an overerase correction pulse is applied to the bitline to which the overerased memory cell is attached. This cycle is repeated until all cells verify as not being overerased. The plurality of memory cells is erase verified and another erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again erase verified. This cycle is repeated until all cells verify as not being undererased. After erase verify is completed, the plurality of memory cells is soft program verified and a soft programming pulse is applied to the those memory cells in the plurality of memory cells which have a threshold voltage below a pre-defined minimum value. This cycle is repeated until all of those memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value are brought above the pre-defined minimum value. The erase method is considered to be finished when there are no memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value.
摘要翻译：提供擦除闪存电可擦除可编程只读存储器（EEPROM）设备的方法，其包括多个存储器单元。擦除脉冲被施加到多个存储单元。多个存储器单元被过度验证，并且过高修正脉冲被施加到被过度存储的存储单元附着的位线。重复此循环，直到所有的单元格都被验证为不被过高。多个存储器单元被擦除验证，并且如果存在未存储的存储器单元并且存储器单元再次被擦除验证，则另一个擦除脉冲被施加到存储器单元。重复此循环，直到所有单元格都被验证为不被忽略。在擦除验证完成之后，多个存储器单元被软件程序验证，并且将软编程脉冲施加到具有低于预定义最小值的阈值电压的多个存储单元中的那些存储单元。重复该循环，直到具有低于预定义最小值的阈值电压的多个存储器单元中的所有那些存储器单元高于预定义的最小值。当多个存储单元中没有存储单元的阈值电压低于预先定义的最小值时，擦除方法被认为是完成的。

3. 发明授权

US06400608B1 Accurate verify apparatus and method for NOR flash memory cells in the presence of high column leakage 有权
标题翻译：在存在高柱泄漏的情况下，NOR闪存单元的精确验证装置和方法
公开(公告)号：US06400608B1
公开(公告)日：2002-06-04
申请号：US09842288
申请日：2001-04-25
申请人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland
发明人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland
IPC分类号： G11C1134
CPC分类号： G11C16/3422 , G11C16/344 , G11C16/3445
摘要： A technique is provided for reducing column leakage in a flash EEPROM device during an erase verification process, thereby preventing false verifies. The technique has application in NOR arrays or other types of arrays in which a number of cells are connected in parallel. The technique operates by reducing the leakage of the unselected cells in parallel to the selected cell being verified, thereby preventing false verifies. The technique can also be used in conjunction with other techniques for reducing column leakage, such as soft programming, automatic programming disturb erase (APDE), or various other Vth compacting schemes.
摘要翻译：提供了一种在擦除验证过程中减少闪存EEPROM器件中的列泄漏的技术，从而防止虚假验证。该技术在NOR阵列或其他类型的阵列中的应用，其中多个单元并联连接。该技术通过减少未被选择的小区的泄漏与所验证的所选择的小区并行，从而防止虚假验证来进行操作。该技术还可以与减少列泄漏的其他技术结合使用，例如软编程，自动编程干扰擦除（APDE）或各种其他Vth压缩方案。

4. 发明授权

US06294430B1 Nitridization of the pre-ddi screen oxide 有权
标题翻译： ddi屏幕氧化物的氮化
公开(公告)号：US06294430B1
公开(公告)日：2001-09-25
申请号：US09495213
申请日：2000-01-31
申请人： Richard Fastow , Sameer S. Haddad , Daniel Sobek
发明人： Richard Fastow , Sameer S. Haddad , Daniel Sobek
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/3144 , H01L29/511 , H01L29/7883 , Y10S438/923
摘要： A flash memory device and a method of manufacturing the flash memory device having high reliability in which a gate stack is formed on a tunnel oxide formed on a substrate and a layer of oxide is formed on the surfaces of the gate stack and exposed surfaces of the substrate. Nitrogen is diffused into the layer of oxide.
摘要翻译：闪存器件和制造具有高可靠性的闪速存储器件的方法，其中栅极堆叠形成在形成在衬底上的隧道氧化物上，并且氧化物层形成在栅极堆叠的表面上，基质。氮气扩散到氧化物层中。

5. 发明授权

US06438037B1 Threshold voltage compacting for non-volatile semiconductor memory designs 失效
标题翻译：用于非易失性半导体存储器设计的阈值电压压缩
公开(公告)号：US06438037B1
公开(公告)日：2002-08-20
申请号：US09851773
申请日：2001-05-09
申请人： Richard Fastow , Xin Guo , Sameer S. Haddad
发明人： Richard Fastow , Xin Guo , Sameer S. Haddad
IPC分类号： G11C1606
CPC分类号： G11C16/3409 , G11C16/3404
摘要： A flash memory design with a compact threshold voltage distribution and a method for compacting the threshold voltage for a flash memory design in which the threshold voltage is compacted by erasing a plurality of memory cells to set the threshold voltage for the memory cells substantially towards a median erased threshold voltage; verifying at least one fast-erase memory cell; selectively soft-programming the memory cells; and erasing subsequent to selectively soft-programming.
摘要翻译：具有紧凑阈值电压分布的快闪存储器设计和用于压缩闪速存储器设计的阈值电压的方法，其中阈值电压通过擦除多个存储器单元而被压缩，以将存储器单元的阈值电压基本上朝向中位数擦除阈值电压; 验证至少一个快速擦除存储器单元; 选择性地软编程存储器单元; 并且在选择性软编程之后擦除。

6. 发明授权

US06469939B1 Flash memory device with increase of efficiency during an APDE (automatic program disturb after erase) process 有权
标题翻译：闪存器件在APDE期间提高效率（擦除后的自动程序干扰）过程
公开(公告)号：US06469939B1
公开(公告)日：2002-10-22
申请号：US09969572
申请日：2001-10-01
申请人： Zhigang Wang , Richard Fastow , Sheung-Hee Park , Sameer S. Haddad , Chi Chang
发明人： Zhigang Wang , Richard Fastow , Sheung-Hee Park , Sameer S. Haddad , Chi Chang
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/12 , G11C16/3404
摘要： A source resistor or a positive voltage is coupled to the source and a negative bias voltage is applied at the substrate or p-well of flash memory cells for enhanced efficiency during programming and/or during an APDE (Automatic Program Disturb after Erase) process for a flash memory device. Furthermore, in a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected.
摘要翻译：源极电阻或正电压耦合到源极，并且在闪存单元的衬底或p阱处施加负偏置电压，以在编程期间和/或在APDE（擦除后自动程序干扰）处理期间提高效率闪存设备。此外，在用于对闪速存储器件进行编程的系统和方法中，选择多个闪速存储器单元的阵列中的闪存单元进行编程。控制栅极编程电压被施加到所选择的闪速存储器单元的控制栅极，并且位线编程电压通过公共位线端子被施加到所选择的闪存单元的漏极，所述公共位线端子选择闪存的漏极单元格已连接。

7. 发明授权

US06452840B1 Feedback method to optimize electric field during channel erase of flash memory devices 有权
标题翻译：用于优化闪存器件通道擦除期间电场的反馈方法
公开(公告)号：US06452840B1
公开(公告)日：2002-09-17
申请号：US09693649
申请日：2000-10-21
申请人： Ravi S. Sunkavalli , Lee Cleveland , Sameer S. Haddad , Richard Fastow , Tim Thurgate
发明人： Ravi S. Sunkavalli , Lee Cleveland , Sameer S. Haddad , Richard Fastow , Tim Thurgate
IPC分类号： G11C1604
CPC分类号： G11C16/3477 , G11C16/344 , G11C16/3445 , G11C16/3472
摘要： A method of erasing a flash memory device that improves reliability and reduces the decrease in erase speed. The state of erasure is determined either during an erase phase or a verify phase and the information is fedback to a controller that adjusts the erase vertical electrical field that is to be applied to the array. The vertical electrical field is adjusted by changing the gate voltage, the well voltage or changing both simultaneously.
摘要翻译：一种擦除闪速存储器件的方法，其提高可靠性并减少擦除速度的降低。在擦除阶段或验证阶段期间确定擦除状态，并将信息反馈到调整要应用于阵列的擦除垂直电场的控制器。通过改变栅极电压，井电压或同时改变两者来调节垂直电场。

8. 发明授权

US06773990B1 Method for reducing short channel effects in memory cells and related structure 有权
标题翻译：减少存储单元短路效应的方法及相关结构
公开(公告)号：US06773990B1
公开(公告)日：2004-08-10
申请号：US10429150
申请日：2003-05-03
申请人： Richard Fastow , Yue-Song He , Kazuhiro Mizutani , Timothy Thurgate
发明人： Richard Fastow , Yue-Song He , Kazuhiro Mizutani , Timothy Thurgate
IPC分类号： H10L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region. The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region.
摘要翻译：根据一个示例性实施例，一种用于制造浮动栅极存储器阵列的方法包括从位于衬底中的隔离区域去除介电材料以暴露沟槽的步骤，其中沟槽位于第一源区域和第二源极之间区域，其中沟槽限定衬底中的侧壁。该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入N型掺杂剂，其中N型掺杂剂形成N +型区域。该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入P型掺杂剂，其中P型掺杂剂形成P型区域，并且其中P型区域位于N +型下方地区。

9. 发明授权

US07301193B2 Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元中低Vss电阻和减少DIBL的结构和方法
公开(公告)号：US07301193B2
公开(公告)日：2007-11-27
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

10. 发明申请

US20050164450A1 Structure and method for low Vss resistance and reduced dibl in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元的低Vss电阻和二极管的结构和方法
公开(公告)号：US20050164450A1
公开(公告)日：2005-07-28
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L21/28 , H01L21/336 , H01L21/74 , H01L29/417 , H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式