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1. 发明授权

US08031528B2 Flash memory programming and verification with reduced leakage current 有权
标题翻译：闪存编程和验证，减少漏电流
公开(公告)号：US08031528B2
公开(公告)日：2011-10-04
申请号：US12557721
申请日：2009-09-11
申请人： Ashot Melik-Martirosian , Ed Runnion , Mark Randolph , Meng Ding
发明人： Ashot Melik-Martirosian , Ed Runnion , Mark Randolph , Meng Ding
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0475 , G11C16/12 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459
摘要： A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.
摘要翻译：根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。

2. 发明申请

US20100314753A1 SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING 有权
标题翻译：减少过程诱发电荷的系统和方法
公开(公告)号：US20100314753A1
公开(公告)日：2010-12-16
申请号：US12860074
申请日：2010-08-20
申请人： Ashot Melik MARTIROSIAN , Zhizheng LIU , Mark RANDOLPH
发明人： Ashot Melik MARTIROSIAN , Zhizheng LIU , Mark RANDOLPH
IPC分类号： H01L23/48
CPC分类号： H01L21/76838 , H01L21/76816 , H01L27/11521
摘要： A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.
摘要翻译：半导体器件包括衬底，形成在衬底上的存储单元和与衬底的接触。接触形成在远离存储单元的区域中，起到提高衬底电位的作用。

3. 发明申请

US20090189212A1 ELECTRONIC DEVICE HAVING A DOPED REGION WITH A GROUP 13 ATOM 审中-公开
标题翻译：具有第13组ATOP的区域的电子设备
公开(公告)号：US20090189212A1
公开(公告)日：2009-07-30
申请号：US12022795
申请日：2008-01-30
申请人： Gwyn Robert Jones , Mark Randolph
发明人： Gwyn Robert Jones , Mark Randolph
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： An electronic device includes a memory cell. The memory cell includes a semiconductor region, a first current-carrying electrode adjacent to the semiconductor region, and a first dopant-containing region adjacent to a first current-carrying electrode. The semiconductor region includes a Group 14 atom and the first dopant-containing region includes a Group 13 atom. The Group 13 atom has an atomic number greater than the atomic number of the Group 14 atom.
摘要翻译：电子设备包括存储单元。存储单元包括半导体区域，与半导体区域相邻的第一载流电极和与第一载流电极相邻的第一掺杂剂区域。半导体区域包括第14族原子，第一掺杂剂区域包括第13族原子。第13族原子的原子数大于第14族原子的原子数。

4. 发明申请

US20090155992A1 HIGH K STACK FOR NON-VOLATILE MEMORY 有权
标题翻译：用于非易失性存储器的高K堆叠
公开(公告)号：US20090155992A1
公开(公告)日：2009-06-18
申请号：US12351553
申请日：2009-01-09
申请人： Wei ZHENG , Mark RANDOLPH , Hidehiko SHIRAIWA
发明人： Wei ZHENG , Mark RANDOLPH , Hidehiko SHIRAIWA
IPC分类号： H01L21/28
CPC分类号： H01L29/792 , G11C16/0475 , H01L21/28273 , H01L21/28282
摘要： A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.
摘要翻译：存储器件可以包括形成在衬底中的源极区域和漏极区域以及形成在源极和漏极区域之间的衬底中的沟道区域。存储器件还可以包括形成在沟道区上的第一氧化物层，第一氧化物层具有第一介电常数，以及形成在第一氧化物层上的电荷存储层。存储器件还可以包括形成在电荷存储层上的第二氧化物层，形成在第二氧化物层上的介电材料层，介电材料具有大于第一介电常数的第二介电常数，以及栅电极形成在电介质材料层上。

5. 发明申请

US20080123384A1 SELECT TRANSISTOR USING BURIED BIT LINE FROM CORE 有权
标题翻译：选择晶体管使用来自核心的BIT线
公开(公告)号：US20080123384A1
公开(公告)日：2008-05-29
申请号：US11465701
申请日：2006-08-18
申请人： Mark RANDOLPH , Zhizheng LIU , Ashot MELIK-MARTIROSIAN , Yi HE , Shankar SINHA
发明人： Mark RANDOLPH , Zhizheng LIU , Ashot MELIK-MARTIROSIAN , Yi HE , Shankar SINHA
IPC分类号： G11C5/02
CPC分类号： G11C5/063 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in the core memory array and with substantially the same channel length.
摘要翻译：半导体器件包括核心存储器阵列和周边区域。核心存储器阵列区域包括一组存储器单元。外围区域包括一组选择晶体管。选择晶体管以与芯存储器阵列中的存储器单元基本相同的间距形成并具有基本上相同的沟道长度。

6. 发明授权

US07262095B1 System and method for reducing process-induced charging 有权
标题翻译：减少过程引发充电的系统和方法
公开(公告)号：US07262095B1
公开(公告)日：2007-08-28
申请号：US11146126
申请日：2005-06-07
申请人： Ashot Melik Martirosian , Zhizheng Liu , Mark Randolph
发明人： Ashot Melik Martirosian , Zhizheng Liu , Mark Randolph
IPC分类号： H01L21/336
CPC分类号： H01L21/76838 , H01L21/76816 , H01L27/11521
摘要： A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate.
摘要翻译：半导体器件包括衬底，形成在衬底上的存储单元和与衬底的接触。接触形成在远离存储单元的区域中，起到提高衬底电位的作用。

7. 发明授权

US07170796B1 Methods and systems for reducing the threshold voltage distribution following a memory cell erase 有权
标题翻译：减少存储单元擦除后阈值电压分布的方法和系统
公开(公告)号：US07170796B1
公开(公告)日：2007-01-30
申请号：US11193391
申请日：2005-08-01
申请人： Yi He , Gwyn Jones , Edward F. Runnion , Mark Randolph
发明人： Yi He , Gwyn Jones , Edward F. Runnion , Mark Randolph
IPC分类号： G11C11/34
CPC分类号： G11C16/14 , G11C16/3468 , G11C16/3472 , G11C16/3477
摘要： A method is provided for erasing a memory device including a number of memory cells, the memory cells including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes erasing a group of memory cells to lower a maximum threshold voltage of the group of memory cells below a first predetermined level. The group of memory cells is soft-programmed to raise a minimum threshold voltage of the group of memory cells above a second predetermined level. The group of memory cells is erased, following soft-programming, resulting in a reduced threshold voltage distribution associated with the group of memory cells.
摘要翻译：提供了一种用于擦除包括多个存储单元的存储器件的方法，所述存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。该方法包括擦除一组存储器单元以将存储器单元组的最大阈值电压降低到低于第一预定水平。存储器单元组被软编程以将存储器单元组的最小阈值电压提高到高于第二预定水平。在软编程之后，存储单元组被擦除，导致与该组存储器单元相关联的阈值电压分布降低。

8. 发明授权

US07167398B1 System and method for erasing a memory cell 有权
标题翻译：擦除存储单元的系统和方法
公开(公告)号：US07167398B1
公开(公告)日：2007-01-23
申请号：US11062641
申请日：2005-02-23
申请人： Zhizheng Liu , Satoshi Torii , Mark Randolph , Yi He
发明人： Zhizheng Liu , Satoshi Torii , Mark Randolph , Yi He
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0475 , G11C16/14 , H01L29/66833 , H01L29/7923
摘要： A method erases a memory cell of a semiconductor device that includes a group of memory cells. Each memory cell includes a group of storage regions. The method includes determining that each storage region of the group of storage regions of a first memory cell is to be erased and erasing the group of storage regions of the first memory cell via a single hot hole injection process.
摘要翻译：一种方法擦除包括一组存储单元的半导体器件的存储单元。每个存储单元包括一组存储区域。该方法包括：通过单个热孔注入处理确定要擦除第一存储器单元组的存储区域的每个存储区域并擦除第一存储单元的存储区域组。

9. 发明申请

US20060151821A1 Memory device having trapezoidal bitlines and method of fabricating same 有权
公开(公告)号：US20060151821A1
公开(公告)日：2006-07-13
申请号：US11033588
申请日：2005-01-12
申请人： Ashot Melik-Martirosian , Mark Ramsbey , Mark Randolph
发明人： Ashot Melik-Martirosian , Mark Ramsbey , Mark Randolph
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.

10. 发明授权

US06994876B1 Iron fortification system 失效
标题翻译：铁强化系统
公开(公告)号：US06994876B1
公开(公告)日：2006-02-07
申请号：US09914880
申请日：2000-03-01
申请人： Alexander Sher , Mark Randolph Jacobson , Chandrasekhara Reddy Mallangi , Dharam Vir Vadehra , Elaine Regina Wedral
发明人： Alexander Sher , Mark Randolph Jacobson , Chandrasekhara Reddy Mallangi , Dharam Vir Vadehra , Elaine Regina Wedral
IPC分类号： A23L1/304 , A23L2/00
CPC分类号： A23L2/52 , A23C9/1522 , A23L33/165 , A23L33/18 , A23L33/40 , A23V2002/00 , A23V2250/1592
摘要： An iron-protein hydrolysate complex which may be used to fortify foods and beverages with iron. The complex is formed of ferrous ions chelated to partially hydrolyzed egg white protein. The hydrolyzed egg white protein has a molecular weight in the range of about 500 to about 10,000. The complexes are sufficiently stable as to be suitable for use in sterilized products, such as retorted products. Moreover, despite the stability, the iron in the complexes has substantially the same bioavailability as ferrous sulfate.
摘要翻译：铁蛋白水解物配合物，可用于加强铁食品和饮料。该复合物由螯合部分水解蛋白蛋白质的亚铁离子形成。水解的蛋白蛋白质的分子量在约500至约10,000的范围内。络合物足够稳定，适用于灭菌产品，如蒸馏产品。此外，尽管稳定性，配合物中的铁具有与硫酸亚铁基本上相同的生物利用度。

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