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1. 发明授权

US06911704B2 Memory cell array with staggered local inter-connect structure 失效
公开(公告)号：US06911704B2
公开(公告)日：2005-06-28
申请号：US10685044
申请日：2003-10-14
申请人： Mark W. Randolph , Sameer S. Haddad , Timothy Thurgate , Richard Fastow
发明人： Mark W. Randolph , Sameer S. Haddad , Timothy Thurgate , Richard Fastow
IPC分类号： G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L27/082
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521
摘要： A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.

2. 发明授权

US06795357B1 Method for reading a non-volatile memory cell 失效
标题翻译：读取非易失性存储单元的方法
公开(公告)号：US06795357B1
公开(公告)日：2004-09-21
申请号：US10283590
申请日：2002-10-30
申请人： Zhizheng Liu , Yi He , Mark W. Randolph , Sameer S. Haddad
发明人： Zhizheng Liu , Yi He , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C700
CPC分类号： G11C16/0491 , G11C16/0475 , G11C16/26
摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a source voltage to a first bit line that is the source of the selected memory cell and applying a drain voltage to a second bit line that forms a drain junction with the channel region. The source voltage may be a small positive voltage and the drain voltage may be greater than the source voltage. A read voltage is applied to a selected one of the word lines that forms a gate over the charge storage region and a bias voltage is applied to non-selected word lines in the array. The bias voltage may be a negative voltage.
摘要翻译：检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括将源电压施加到作为所选存储单元的源的第一位线并施加到与沟道区形成漏极结的第二位线的漏极电压。源极电压可以是小的正电压，并且漏极电压可能大于源极电压。将读取电压施加到在电荷存储区域上形成栅极的所选择的一条字线，并且将偏置电压施加到阵列中的未选择的字线。偏置电压可以是负电压。

3. 发明授权

US06862221B1 Memory device having a thin top dielectric and method of erasing same 有权
标题翻译：具有薄顶电介质的存储器件及其擦除方法
公开(公告)号：US06862221B1
公开(公告)日：2005-03-01
申请号：US10459102
申请日：2003-06-11
申请人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
发明人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C16/04 , H01L21/28 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , G11C16/0475 , H01L29/42324 , H01L29/7887 , H01L29/7923
摘要： A non-volatile memory device includes a semiconductor substrate and a source and drain within the substrate. A dielectric stack is formed over the substrate. The dielectric stack includes a thin top dielectric layer. A gate electrode is formed over the dielectric stack. The memory device is operative to perform a direct tunneling channel erase operation in which a pair of charge storing cells within a charge storing layer are erased via direct tunneling through the thin top dielectric layer.
摘要翻译：非易失性存储器件包括半导体衬底和衬底内的源极和漏极。在衬底上形成电介质叠层。电介质堆叠包括薄的顶部电介质层。在电介质叠层上形成栅电极。存储器装置可操作以执行直接隧道通道擦除操作，其中电荷存储层内的一对电荷存储单元通过经由薄顶介电层的直接隧穿而被擦除。

4. 发明授权

US06868014B1 Memory device with reduced operating voltage having dielectric stack 有权
标题翻译：具有电介质叠层的具有降低工作电压的存储器
公开(公告)号：US06868014B1
公开(公告)日：2005-03-15
申请号：US10430604
申请日：2003-05-06
申请人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
发明人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C16/04 , H01L21/28 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7923 , H01L21/28282 , H01L29/42324 , H01L29/7887
摘要： A non-volatile memory device includes a semiconductor substrate and a pair of buried bitlines within the substrate. A scaled down dielectric stack is formed over the substrate. The scaled down dielectric stack includes a scaled down top dielectric layer, a scaled down charge trapping dielectric layer and a bottom dielectric layer. A wordline is formed over the dielectric stack. The memory device is operative to be programmed using a reduced wordline operating voltage of less than about +8 Volts, and to be erased using a reduced wordline operating voltage of less than about −6 Volts.
摘要翻译：非易失性存储器件包括衬底内的半导体衬底和一对掩埋位线。在衬底上形成按比例缩小的电介质叠层。按比例缩小的电介质堆叠包括按比例缩小的顶部介电层，按比例缩小的电荷俘获电介质层和底部电介质层。在介质叠层上形成一条字线。存储器装置可操作以使用小于约+8伏特的减小的字线工作电压进行编程，并且使用小于约-6伏的减小的字线工作电压来擦除存储器装置。

5. 发明授权

US06795342B1 System for programming a non-volatile memory cell 有权
标题翻译：用于编程非易失性存储单元的系统
公开(公告)号：US06795342B1
公开(公告)日：2004-09-21
申请号：US10307667
申请日：2002-12-02
申请人： Yi He , Zhizheng Liu , Mark W. Randolph , Sameer S. Haddad
发明人： Yi He , Zhizheng Liu , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0475 , G11C16/0491
摘要： A system for programming a charge stored on a charge storage region of a dielectric charge trapping layer of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a positive source programming bias to a first bit line that is the source of the selected memory cell while applying a drain programming voltage to a second bit line that forms a drain junction with the channel region and while applying a positive voltage to a selected word line. The source voltage may be applied by coupling the source bit line to a voltage divider or by coupling the source bit line to a resistor which in turn is coupled to a ground. A negative programming bias may also be applied to the substrate and to unselected word lines.
摘要翻译：一种用于对存储在双位介质存储器单元阵列内的第一双位介质存储单元的介电电荷俘获层的电荷存储区域上的电荷进行编程的系统包括将正源编程偏置施加到第一位线同时将漏极编程电压施加到与沟道区形成漏极结的第二位线以及向所选择的字线施加正电压的所选存储单元的源极。可以通过将源极线耦合到分压器或通过将源极线耦合到电阻器来施加源极电压，电阻器又连接到地电位器。负编程偏置也可以应用于衬底和未选择的字线。

6. 发明授权

US06894932B1 Dual cell memory device having a top dielectric stack 有权
标题翻译：具有顶部电介质叠层的双电池存储器件
公开(公告)号：US06894932B1
公开(公告)日：2005-05-17
申请号：US10716230
申请日：2003-11-18
申请人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
发明人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/06 , H01L27/115 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0475 , H01L21/28273 , H01L27/0688 , H01L27/115 , H01L27/11578 , H01L29/512 , H01L29/517 , H01L29/66833 , H01L29/7923
摘要： A non-volatile memory device includes a semiconductor substrate and a pair of buried bitlines within the substrate. A bottom dielectric layer is formed over the substrate and a charge trapping dielectric layer is formed over the bottom dielectric layer. A multi-layer top dielectric stack is formed over the charge trapping dielectric layer. The top dielectric stack includes a first oxide layer, a nitride layer, and a second oxide layer. A wordline is formed over the top dielectric stack. The multi-layer top dielectric stack has a reduced electrical thickness, thereby providing a memory device, which is operative to be programmed using a reduced operating voltage of less than about +8 Volts.
摘要翻译：非易失性存储器件包括衬底内的半导体衬底和一对掩埋位线。底部电介质层形成在衬底上，并且电荷俘获电介质层形成在底部电介质层上。在电荷捕获介电层上形成多层顶层电介质叠层。顶部电介质堆叠包括第一氧化物层，氮化物层和第二氧化物层。在顶部电介质叠层上形成字线。多层顶部电介质堆叠具有减小的电气厚度，从而提供存储器件，其可操作地使用小于约+8伏特的降低的工作电压进行编程。

7. 发明授权

US06735124B1 Flash memory device having four-bit cells 失效
标题翻译：具有四位单元的闪存器件
公开(公告)号：US06735124B1
公开(公告)日：2004-05-11
申请号：US10315632
申请日：2002-12-10
申请人： Ashot Melik-Martirosian , Sameer S. Haddad , Mark W. Randolph
发明人： Ashot Melik-Martirosian , Sameer S. Haddad , Mark W. Randolph
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5671
摘要： A non-volatile memory device includes a semiconductor substrate having first and second bitlines buried therein. The first bitline serves as a source terminal and the second bitline serves as a drain terminal. An oxide-nitride-oxide (ONO) stack is formed over the substrate. The ONO stack includes a charge storing layer having at least four charge storing cells therein. A pair of complementary conductive regions are disposed on opposite sides of the ONO stack extending in a direction perpendicular to the first and second bitlines. A wordline, which serves as a gate electrode, is disposed above the ONO stack and laterally between the first and second complementary conductive regions.
摘要翻译：非易失性存储器件包括其中埋有第一和第二位线的半导体衬底。第一位线用作源极端子，第二位线用作漏极端子。在衬底上形成氧化物 - 氧化物 - 氧化物（ONO）堆叠。 ONO堆叠包括其中具有至少四个电荷存储单元的电荷存储层。一对互补导电区域设置在ONO堆叠的相对两侧，该垂直于第一和第二位线的方向延伸。用作栅电极的字线布置在ONO堆叠之上，并且横向地设置在第一和第二互补导电区域之间。

8. 发明授权

US06735114B1 Method of improving dynamic reference tracking for flash memory unit 有权
标题翻译：改进闪存单元动态参考跟踪的方法
公开(公告)号：US06735114B1
公开(公告)日：2004-05-11
申请号：US10357879
申请日：2003-02-04
申请人： Darlene G. Hamilton , Eric M. Ajimine , Ming-Huei Shieh , Lee Cleveland , Edward F. Runnion , Mark W. Randolph , Sameer S. Haddad
发明人： Darlene G. Hamilton , Eric M. Ajimine , Ming-Huei Shieh , Lee Cleveland , Edward F. Runnion , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C1604
CPC分类号： G11C16/3418 , G11C16/0475 , G11C16/28
摘要： A method of programming a memory unit having a plurality of dual cell core memory devices and at least one dual cell dynamic reference device. The memory unit is subjected to an erase configuration operation such that each cell of the core memory devices is in a blank state and such that a threshold voltage of the at least one dynamic reference device is less than a charged program level threshold voltage. Thereafter, the at least one dynamic reference and the core memory devices are programmed using a page programming routine.
摘要翻译：一种编程具有多个双单元核心存储器件和至少一个双单元动态参考器件的存储器单元的方法。对存储器单元进行擦除配置操作，使得核心存储器件的每个单元处于空白状态，并且使得至少一个动态参考器件的阈值电压小于充电的程序电平阈值电压。此后，使用页面编程例程对至少一个动态参考和核心存储器设备进行编程。

9. 发明授权

US06653189B1 Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory 有权
标题翻译：源极硼注入和漏极侧MDD植入物用于深亚0.18微米闪存
公开(公告)号：US06653189B1
公开(公告)日：2003-11-25
申请号：US09699711
申请日：2000-10-30
申请人： Sameer Haddad , Yue-song He , Timothy Thurgate , Chi Chang , Mark W. Randolph , Ngaching Wong
发明人： Sameer Haddad , Yue-song He , Timothy Thurgate , Chi Chang , Mark W. Randolph , Ngaching Wong
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L29/66833
摘要： One aspect of the present invention relates to a method of making a flash memory cell, involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; forming a MDD mask over the substrate, the MDD mask covering the source lines and having openings corresponding to drain lines; and implanting a medium dosage drain implant of a second type to form a drain region in the substrate adjacent the flash memory cell.
摘要翻译：本发明的一个方面涉及一种制造闪存单元的方法，包括以下步骤：在其上提供闪存单元; 在衬底上形成自对准源掩模，所述自对准源掩模具有对应于源极线的开口; 通过对应于源极线的自对准源掩模中的开口将衬底中的第一类型源掺杂剂注入到衬底中; 从衬底去除自对准源掩模; 在衬底上形成MDD掩模，MDD掩模覆盖源极线并具有对应于漏极线的开口; 以及植入第二类型的介质剂量漏极注入，以在与所述闪存单元相邻的所述衬底中形成漏极区域。

10. 发明授权

US07995386B2 Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb 有权
标题翻译：将负栅极电压施加到与读取或验证相关的字线附近的字线，以减少相邻的字线干扰
公开(公告)号：US07995386B2
公开(公告)日：2011-08-09
申请号：US12275663
申请日：2008-11-21
申请人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
发明人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/08 , G11C16/3427
摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.
摘要翻译：提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

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