专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07301193B2 Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元中低Vss电阻和减少DIBL的结构和方法
公开(公告)号：US07301193B2
公开(公告)日：2007-11-27
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

2. 发明申请

US20050164450A1 Structure and method for low Vss resistance and reduced dibl in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元的低Vss电阻和二极管的结构和方法
公开(公告)号：US20050164450A1
公开(公告)日：2005-07-28
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L21/28 , H01L21/336 , H01L21/74 , H01L29/417 , H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

3. 发明授权

US08208296B2 Apparatus and method for extended nitride layer in a flash memory 有权
标题翻译：闪存中的延伸氮化物层的装置和方法
公开(公告)号：US08208296B2
公开(公告)日：2012-06-26
申请号：US12706710
申请日：2010-02-16
申请人： Timothy Thurgate , Shenqing Fang , Kuo Tung Chang , Youseok Suh
发明人： Timothy Thurgate , Shenqing Fang , Kuo Tung Chang , Youseok Suh
IPC分类号： G11C11/34
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11568 , H01L29/66833
摘要： A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulator disposed above the source/drain region. The charge trapping layer is within the insulator, and the charge trapping layer is above the entire width of the source/drain region, and extends at least one angstrom beyond the width of the source/drain region, so that a portion the charge trapping layer extends into at least one shallow trench.
摘要翻译：提供了一种用于存储信息的方法和装置。存储器的核心区域包括半导体层，至少一个浅沟槽，绝缘体和电荷俘获层。半导体层包括至少一个源极/漏极区域，以及设置在源极/漏极区域上方的绝缘体。电荷捕获层在绝缘体内，并且电荷捕获层高于源/漏区的整个宽度，并且延伸超过源极/漏极区的宽度至少一埃，使得电荷捕获层延伸到至少一个浅沟槽中。

4. 发明授权

US08076712B2 Semiconductor memory comprising dual charge storage nodes and methods for its fabrication 有权
标题翻译：半导体存储器包括双电荷存储节点及其制造方法
公开(公告)号：US08076712B2
公开(公告)日：2011-12-13
申请号：US12840165
申请日：2010-07-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
发明人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
IPC分类号： H01L29/788
CPC分类号： H01L29/42332 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.
摘要翻译：提供了双电荷存储节点存储器件及其制造方法。在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。在第二部分上形成一层半导体材料。第一层状结构形成在电介质塞的第二部分的第一侧上，并且第二层结构形成在第二侧上，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层和第二电介质层。将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

5. 发明授权

US07767517B2 Semiconductor memory comprising dual charge storage nodes and methods for its fabrication 有权
标题翻译：半导体存储器包括双电荷存储节点及其制造方法
公开(公告)号：US07767517B2
公开(公告)日：2010-08-03
申请号：US11613513
申请日：2006-12-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
发明人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
IPC分类号： H01L21/8242
CPC分类号： H01L29/42332 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.
摘要翻译：提供了双电荷存储节点存储器件及其制造方法。在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。在第二部分上形成一层半导体材料。第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层和第二电介质层。将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

6. 发明授权

US07696038B1 Methods for fabricating flash memory devices 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US07696038B1
公开(公告)日：2010-04-13
申请号：US11412365
申请日：2006-04-26
申请人： Ning Cheng , Kuo-Tung Chang , Hiroyuki Kinoshita , Timothy Thurgate , Wei Zheng , Ashot Melik-Martirosian , Angela Hui , Chih-Yuh Yang
发明人： Ning Cheng , Kuo-Tung Chang , Hiroyuki Kinoshita , Timothy Thurgate , Wei Zheng , Ashot Melik-Martirosian , Angela Hui , Chih-Yuh Yang
IPC分类号： H01L21/8238
CPC分类号： H01L27/11568 , G11C16/3418 , G11C16/3427
摘要： Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.
摘要翻译：提供了制造闪速存储器件的方法。根据本发明的示例性实施例，一种用于制造存储器件的方法包括形成覆盖衬底的第一栅极堆叠和第二栅极堆叠。在第一栅极堆叠和第二栅极堆叠之间的沟槽被蚀刻到衬底中。第一杂质掺杂区域形成在沟槽下面的衬底内。

7. 发明申请

US20080149999A1 SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION 有权
标题翻译：包含双电池存储器的半导体存储器及其制造方法
公开(公告)号：US20080149999A1
公开(公告)日：2008-06-26
申请号：US11613513
申请日：2006-12-20
申请人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
发明人： Chungho Lee , Ashot Melik-Martirosian , Wei Zheng , Timothy Thurgate , Chi Chang , Hiroyuki Kinoshita , Kuo-Tung Chang , Unsoon Kim
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/42332 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42348 , H01L29/7887 , H01L29/7923
摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.
摘要翻译：提供了双电荷存储节点存储器件及其制造方法。在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。在第二部分上形成一层半导体材料。第一层状结构形成在电介质塞的第二部分的第一侧上，并且形成在第二侧上的第二层状结构，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层和第二电介质层。将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。

8. 发明授权

US06773990B1 Method for reducing short channel effects in memory cells and related structure 有权
标题翻译：减少存储单元短路效应的方法及相关结构
公开(公告)号：US06773990B1
公开(公告)日：2004-08-10
申请号：US10429150
申请日：2003-05-03
申请人： Richard Fastow , Yue-Song He , Kazuhiro Mizutani , Timothy Thurgate
发明人： Richard Fastow , Yue-Song He , Kazuhiro Mizutani , Timothy Thurgate
IPC分类号： H10L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region. The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region.
摘要翻译：根据一个示例性实施例，一种用于制造浮动栅极存储器阵列的方法包括从位于衬底中的隔离区域去除介电材料以暴露沟槽的步骤，其中沟槽位于第一源区域和第二源极之间区域，其中沟槽限定衬底中的侧壁。该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入N型掺杂剂，其中N型掺杂剂形成N +型区域。该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入P型掺杂剂，其中P型掺杂剂形成P型区域，并且其中P型区域位于N +型下方地区。

9. 发明授权

US06963106B1 Memory array with memory cells having reduced short channel effects 有权
标题翻译：具有存储单元的存储器阵列具有减少的短通道效应
公开(公告)号：US06963106B1
公开(公告)日：2005-11-08
申请号：US10839626
申请日：2004-05-04
申请人： Richard Fastow , Yue-Song He , Kazuhiro Mizutani , Timothy Thurgate
发明人： Richard Fastow , Yue-Song He , Kazuhiro Mizutani , Timothy Thurgate
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region. The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region.
摘要翻译：根据一个示例性实施例，一种用于制造浮动栅极存储器阵列的方法包括从位于衬底中的隔离区域去除介电材料以暴露沟槽的步骤，其中沟槽位于第一源区域和第二源极之间区域，其中沟槽限定衬底中的侧壁。该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入N型掺杂剂，其中N型掺杂剂形成N +型区域。该方法还包括在第一源极区域，第二源极区域和沟槽的侧壁中注入P型掺杂剂，其中P型掺杂剂形成P型区域，并且其中P型区域位于N +型下方地区。

10. 发明申请

US20100208527A1 SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS IN ELECTROMAGNETIC FIELDS DURING ERASE OF NONVOLATILE MEMORY 有权
标题翻译：选择性应用字线偏移以最小化非易失性存储器中的电磁场中的影响
公开(公告)号：US20100208527A1
公开(公告)日：2010-08-19
申请号：US12773232
申请日：2010-05-04
申请人： Gulzar Ahmed Kathawala , Wei Zheng , Zhizheng Liu , Sung-Yong Chung , Timothy Thurgate , Kuo-Tung Chang , Sheung-Hee Park , Gabrielle Wing Han Leung
发明人： Gulzar Ahmed Kathawala , Wei Zheng , Zhizheng Liu , Sung-Yong Chung , Timothy Thurgate , Kuo-Tung Chang , Sheung-Hee Park , Gabrielle Wing Han Leung
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.
摘要翻译：提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元当存储器单元是端行存储单元时。优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应在擦除期间应用于细胞。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式