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1. 发明授权

US5999452A Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for NAND array flash memory 失效
标题翻译：双源多晶硅选择门结构和编程方法，利用单隧道氧化物进行NAND阵列闪存
公开(公告)号：US5999452A
公开(公告)日：1999-12-07
申请号：US63688
申请日：1998-04-21
申请人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
发明人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C16/0483
摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
摘要翻译：串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。串联选择晶体管连接到NAND串中的最后一个晶体管。源选择晶体管连接到阵列Vss电源。为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

2. 发明授权

US5912489A Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory 失效
标题翻译：双源端多晶硅选择门结构利用单隧道氧化物用于NAND阵列闪存
公开(公告)号：US5912489A
公开(公告)日：1999-06-15
申请号：US940674
申请日：1997-09-30
申请人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
发明人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483
摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
摘要翻译：串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。串联选择晶体管连接到NAND串中的最后一个晶体管。源选择晶体管连接到阵列Vss电源。为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

3. 发明授权

US06266275B1 Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for nand array flash memory 有权
标题翻译：双源多晶硅选择门结构和编程方法，利用单隧道氧化物进行阵列闪存存储
公开(公告)号：US06266275B1
公开(公告)日：2001-07-24
申请号：US09410512
申请日：1999-09-30
申请人： Paul-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
发明人： Paul-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
IPC分类号： G11C700
CPC分类号： G11C16/0483
摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
摘要翻译：串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。串联选择晶体管连接到NAND串中的最后一个晶体管。源选择晶体管连接到阵列Vss电源。为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

4. 发明授权

US5844840A High voltage NMOS pass gate having supply range, area, and speed advantages 失效
标题翻译：具有供电范围，面积和速度优势的高压NMOS通道门
公开(公告)号：US5844840A
公开(公告)日：1998-12-01
申请号：US914543
申请日：1997-08-19
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
IPC分类号： G11C8/08 , G11C16/06
CPC分类号： G11C8/08
摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.
摘要翻译：根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管阈值电压实际上驱动到字线上。根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。

5. 发明授权

US5909396A High voltage NMOS pass gate having supply range, area, and speed advantages 有权
标题翻译：具有供电范围，面积和速度优势的高压NMOS通道门
公开(公告)号：US5909396A
公开(公告)日：1999-06-01
申请号：US127991
申请日：1998-08-03
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
IPC分类号： G11C8/08 , G11C16/06
CPC分类号： G11C8/08
摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistor's threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.
摘要翻译：根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管的阈值电压实际上驱动到字线上。根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。

6. 发明授权

US5793677A Using floating gate devices as select gate devices for NAND flash memory and its bias scheme 失效
标题翻译：使用浮动栅极器件作为NAND闪存的选择栅极器件及其偏置方案
公开(公告)号：US5793677A
公开(公告)日：1998-08-11
申请号：US668632
申请日：1996-06-18
申请人： Chung-You Hu , Yu Sun , Chi Chang , Sameer Haddad
发明人： Chung-You Hu , Yu Sun , Chi Chang , Sameer Haddad
IPC分类号： G11C16/04 , G11C13/00 , H01L27/115
CPC分类号： G11C16/0483
摘要： The present invention facilitates programming of selected floating gate devices while successfully inhibiting the programming of unselected devices, without the need for growing multiple thicknesses of oxides. The preferred embodiment of the present invention utilizes a multiple select gate device. In particular, the select gate device is preferably a dual floating gate device rather than the conventional transistor (or device functioning as a conventional transistor) used in the current Flash memory systems as a select gate device.
摘要翻译：本发明有助于编程所选择的浮动栅极器件，同时成功地禁止对未选择器件的编程，而不需要生长多个厚度的氧化物。本发明的优选实施例利用多选择栅极器件。特别地，选择栅极器件优选地是双浮置栅极器件，而不是在当前闪存存储器系统中用作选择栅极器件的常规晶体管（或用作常规晶体管的器件）。

7. 发明授权

US6009014A Erase verify scheme for NAND flash 失效
标题翻译：擦除NAND闪存的验证方案
公开(公告)号：US6009014A
公开(公告)日：1999-12-28
申请号：US90296
申请日：1998-06-03
申请人： Shane C. Hollmer , Chung-You Hu , Binh Q. Le , Pau-ling Chen , Jonathan Su , Ravi Gutala , Colin Bill
发明人： Shane C. Hollmer , Chung-You Hu , Binh Q. Le , Pau-ling Chen , Jonathan Su , Ravi Gutala , Colin Bill
IPC分类号： G11C16/04 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/344
摘要： The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.
摘要翻译：本发明提供了一种验证NAND串中的所有闪存EEPROM晶体管是否被适当地擦除，而不会通过向NAND阵列的底部选择栅极的源施加偏置电压而对其进行过载并向非线性擦除验证电压施加非负的擦除验证电压在擦除验证期间每个晶体管的控制栅极。偏置电压至少等于最坏情况晶体管的擦除阈值电压，以确保正确的擦除验证。如果所有晶体管都不被擦除，则执行另一个擦除操作。重复擦除直到擦除验证操作指示所有晶体管被正确擦除。通过根据本发明的擦除和验证，NAND阵列被完全和适当地擦除，同时使阵列过度减少。

8. 发明授权

US06438030B1 Non-volatile memory, method of manufacture, and method of programming 有权
标题翻译：非易失性存储器，制造方法和编程方法
公开(公告)号：US06438030B1
公开(公告)日：2002-08-20
申请号：US09639195
申请日：2000-08-15
申请人： Chung-You Hu , Kuo-Tung Chang , Wei-Hua Liu , David Burnett
发明人： Chung-You Hu , Kuo-Tung Chang , Wei-Hua Liu , David Burnett
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/10 , H01L27/115
摘要： A semiconductor device includes a non-volatile memory, such as an electrically erasable programmable read only memory (EEPROM) array of memory cells. The memory is arranged as an array of cells in rows and columns. P-well regions of the array are spaced apart and electrically isolated by shallow trench features. The cells of each column are positioned within a respective isolated p-well region. Control gates of sequentially corresponding memory cells in columns of the array are electrically coupled by common wordlines. Bitlines electrically couple drain regions of each memory cell in the respective columns of the memory cell array. Source lines electrically couple source regions of each memory cell in the respective columns of the array. The source lines and at least one memory cell in each column of the array are electrically coupled to the p-well region corresponding to the column of the source line and cell. Each column of the array is therefore located within an isolated well, common to the cells in the column but isolated from other wells of other columns. The array is programmed by pulsing potentials as to each column, with isolation of results for each column.
摘要翻译：半导体器件包括诸如存储器单元的电可擦除可编程只读存储器（EEPROM）阵列的非易失性存储器。内存被排列成行和列中的单元格数组。阵列的P阱区域被间隔开并且通过浅沟槽特征电隔离。每个柱的细胞位于相应的分离的p阱区内。阵列列中顺序对应的存储单元的控制栅极通过通用字线电耦合。位线电耦合存储器单元阵列的相应列中的每个存储器单元的漏极区域。源极线将阵列的相应列中的每个存储单元的源极区域电耦合。阵列的每列中的源极线和至少一个存储单元电耦合到对应于源极线和单元的列的p阱区。因此，阵列的每列都位于隔离阱中，与柱中的单元通用，但与其他列的其他孔隔离。通过脉冲每个列的电位编程阵列，隔离每列的结果。

9. 发明授权

US5861338A Channel stop implant profile shaping scheme for field isolation 失效
标题翻译：通道停止植入轮廓整形方案进行现场隔离
公开(公告)号：US5861338A
公开(公告)日：1999-01-19
申请号：US786815
申请日：1997-01-21
申请人： Chung-You Hu
发明人： Chung-You Hu
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76216 , Y10S438/981
摘要： The present invention is a semiconductor device and a method of providing such a semiconductor device which allows a high junction breakdown voltage and a high field turn on voltage, while allowing the field oxide thickness to be limited and being independent of a misalignment of the mask. A method in accordance with the present invention for providing a semiconductor device including a field oxide, the field oxide including a field oxide boundary wherein the field oxide is located within the boundary, the method comprising the step of implanting a first implant area into the substrate, including areas proximate indistance to a junction area, the first area being implanted with a first implant concentration and implanting a second implant area distal to the junction area, the second implant area being implanted with a second implant concentration, wherein the depth of the implant is controlled by the energy level, wherein the implant of the second implant area is independent of a misalignment of a mask.
摘要翻译：本发明是提供允许高结击穿电压和高场导通电压的这种半导体器件的半导体器件和方法，同时允许场氧化物厚度被限制并且与掩模的不对准无关。根据本发明的用于提供包括场氧化物的半导体器件的方法，所述场氧化物包括场氧化物边界，其中所述场氧化物位于所述边界内，所述方法包括以下步骤：将第一注入区域注入所述衬底，包括接近于接合区域的区域，所述第一区域被注入第一注入浓度并且在所述接合区域的远端植入第二植入区域，所述第二注入区域被植入第二注入浓度，其中所述植入物的深度由能级控制，其中第二植入区域的植入物与掩模的未对准无关。

10. 发明授权

US5715194A Bias scheme of program inhibit for random programming in a nand flash memory 失效
标题翻译：程序的偏置方案禁止在nand闪存中进行随机编程
公开(公告)号：US5715194A
公开(公告)日：1998-02-03
申请号：US686641
申请日：1996-07-24
申请人： Chung-You Hu
发明人： Chung-You Hu
IPC分类号： G11C16/10 , G11C11/34
CPC分类号： G11C16/10
摘要： The present invention is a system and method which allows random programming and avoids the problem with band-to-band tunneling current discussed above. In particular, the present invention applies a predetermined voltage along the wordlines adjacent to the programming wordline. A method of programming in a Flash memory system includes providing a first wordline coupled with a first device desired to be programmed, the first wordline also coupled with a second device desired to be program inhibited; electrically isolating the second device; programming the first device; and programming a third device coupled with a second wordline, the second wordline not being adjacent to the first wordline.
摘要翻译：本发明是一种允许随机编程并避免上述带 - 带隧道电流问题的系统和方法。特别地，本发明沿着与编程字线相邻的字线应用预定电压。一种在闪速存储器系统中编程的方法包括：提供与期望被编程的第一器件耦合的第一字线，所述第一字线还与希望被禁止编程的第二器件耦合; 电隔离第二装置; 编程第一个设备; 以及编程与第二字线耦合的第三设备，所述第二字线不与所述第一字线相邻。

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