会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for nand array flash memory
    • 双源多晶硅选择门结构和编程方法,利用单隧道氧化物进行阵列闪存存储
    • US06266275B1
    • 2001-07-24
    • US09410512
    • 1999-09-30
    • Paul-Ling ChenMike Van BuskirkShane Charles HollmerBinh Quang LeShoichi KawamuraChung-You HuYu SunSameer HaddadChi Chang
    • Paul-Ling ChenMike Van BuskirkShane Charles HollmerBinh Quang LeShoichi KawamuraChung-You HuYu SunSameer HaddadChi Chang
    • G11C700
    • G11C16/0483
    • A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
    • 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极,串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元,串联选择晶体管的栅极升高到Vcc,同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压,而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。
    • 5. 发明授权
    • Methods for forming nitrogen-rich regions in a floating gate and
interpoly dielectric layer in a non-volatile semiconductor memory device
    • 在非易失性半导体存储器件中的浮栅和互聚电介质层中形成富氮区的方法
    • US6001713A
    • 1999-12-14
    • US154074
    • 1998-09-16
    • Mark T. RamsbeyVei-Han ChanSameer HaddadChi ChangYu SunRaymond Yu
    • Mark T. RamsbeyVei-Han ChanSameer HaddadChi ChangYu SunRaymond Yu
    • H01L21/28H01L21/265
    • H01L21/28273
    • Methods are provided for significantly reducing electron trapping in semiconductor devices having a floating gate and an overlying dielectric layer. The methods form a nitrogen-rich region within the floating gate near the interface to an overlying dielectric layer. The methods include selectively introducing nitrogen into the floating gate prior to forming the overlying dielectric layer. This forms an initial nitrogen concentration profile within the floating gate. An initial portion of the overlying dielectric layer is then formed of a high temperature oxide (HTO). The temperature within the floating gate is purposely raised to an adequately high temperature to cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards the interface with the overlying dielectric layer and an interface with an underlying layer. Consequently, the floating gate is left with a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The first nitrogen-rich region has been found to reduce electron trapping within the floating gate, which could lead to false programming of the floating gate. Unlike a conventional thermally grown oxide film, the high temperature oxide film within the interpoly dielectric layer advantageously prevents the surface of the floating gate from becoming too granular. As such, the resulting interpoly dielectric layer, which typically includes several films, can be formed more evenly.
    • 提供了用于显着减少具有浮置栅极和上覆电介质层的半导体器件中的电子俘获的方法。 该方法在与上覆电介质层的界面附近的浮栅内形成富氮区。 所述方法包括在形成上覆电介质层之前将氮气选择性地引入浮栅。 这在浮动栅极内形成初始氮浓度分布。 然后由上覆电介质层的初始部分由高温氧化物(HTO)形成。 浮置栅极内的温度有意地升高到足够高的温度,以使得初始氮浓度分布由于大部分氮向与上覆介质层的界面的迁移以及与下层的界面而改变。 因此,浮置栅极在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域留下。 已经发现第一个富氮区域减少了浮动栅极内的电子俘获,这可能导致浮动栅极的错误编程。 与传统的热生长氧化膜不同,多聚电介质层内的高温氧化膜有利地防止浮栅的表面变得太细。 因此,可以更均匀地形成通常包括几个膜的所得到的互间介电层。
    • 8. 发明授权
    • Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices
    • 在非易失性半导体存储器件中形成富氮区的方法
    • US06989319B1
    • 2006-01-24
    • US10718707
    • 2003-11-24
    • Mark RamsbeySameer HaddadVei-Han ChanYu SunChi Chang
    • Mark RamsbeySameer HaddadVei-Han ChanYu SunChi Chang
    • H01L21/265
    • H01L21/265H01L21/28176H01L21/28273
    • Methods and arrangements are provided for significantly reducing electron trapping in semiconductor devices having a polysilicon feature and an overlying dielectric layer. The methods and arrangements employ a nitrogen-rich region within the polysilicon feature near the interface to the overlying dielectric layer. The methods include selectively implanting nitrogen ions through at least a portion of the overlying dielectric layer and into the polysilicon feature to form an initial nitrogen concentration profile within the polysilicon feature. Next, the temperature within the polysilicon feature is raised to an adequately high temperature, for example using rapid thermal anneal (RTA) techniques, which cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards either the interface with the overlying dielectric layer or the interface with an underlying layer. Consequently, the polysilicon feature has a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The migration of nitrogen further forms a contiguous reduced-nitrogen region located between the first nitrogen-rich region and the second nitrogen-rich region. The contiguous reduced-nitrogen region has a lower concentration of nitrogen than does the first nitrogen-rich region and the second nitrogen-rich region. The first nitrogen-rich region has been found to reduce electron trapping within the polysilicon feature. Thus, for example, in a non-volatile memory device wherein the polysilicon feature is a floating gate, false programming of the memory device can be significantly avoided by reducing the number of trapped electrons in the floating gate.
    • 提供了用于显着减少具有多晶硅特征和上覆电介质层的半导体器件中的电子俘获的方法和装置。 所述方法和装置在靠近覆盖的介电层的界面附近使用多晶硅特征内的富氮区域。 所述方法包括通过至少部分上覆介质层选择性地注入氮离子并进入多晶硅特征以在多晶硅特征内形成初始氮浓度分布。 接下来,将多晶硅特征中的温度升高到足够高的温度,例如使用快速热退火(RTA)技术,其使得初始氮浓度分布由于大部分氮朝着界面迁移而改变 与上层电介质层或与下层的界面。 因此,多晶硅特征具有在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域。 氮的迁移进一步形成位于第一富氮区和第二富氮区之间的连续的还原氮区。 连续的还原氮区域具有比第一富氮区域和第二富氮区域低的氮浓度。 已发现第一富氮区域减少多晶硅特征内的电子俘获。 因此,例如,在其中多晶硅特征是浮动栅极的非易失性存储器件中,可以通过减少浮置栅极中的俘获电子的数量来显着地避免存储器件的伪编程。