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1. 发明授权

US08498164B1 Variable impedance memory device biasing circuits and methods 有权
标题翻译：可变阻抗存储器件偏置电路和方法
公开(公告)号：US08498164B1
公开(公告)日：2013-07-30
申请号：US13594756
申请日：2012-08-24
申请人： Shane Charles Hollmer , Nad Edward Gilbert
发明人： Shane Charles Hollmer , Nad Edward Gilbert
IPC分类号： G11C7/10
CPC分类号： G11C13/0011 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2213/79
摘要： An integrated circuit can include at least one programmable metallization cell (PMC) comprising an ion conducting material and a metal dissolvable in the ion conducting material, selectively connected to a shunt node; and a biasing circuit comprising a current source coupled to the shunt node configurable to provide a first current in a first type operation, and a voltage regulator coupled to the shunt node configured to regulate a potential at the shunt node; wherein in the first type operation, the voltage regulator shunts current with respect to the shunt node in a same direction as a current flow of the at least one PMC.
摘要翻译：集成电路可以包括至少一个可编程金属化单元（PMC），该可编程金属化单元包括离子传导材料和可溶于离子传导材料的金属，选择性地连接到分流节点; 以及偏置电路，其包括耦合到所述分流节点的电流源，所述电流源可配置为在第一类型操作中提供第一电流，以及耦合到所述分流节点的电压调节器，被配置为调节所述分流节点处的电位; 其中在所述第一类型操作中，所述电压调节器以与所述至少一个PMC的电流相同的方向将相对于所述分流节点的电流分流。

2. 发明授权

US06593606B1 Staggered bitline strapping of a non-volatile memory cell 失效
标题翻译：非易失性存储单元的交错位线捆扎
公开(公告)号：US06593606B1
公开(公告)日：2003-07-15
申请号：US09718771
申请日：2000-11-22
申请人： Mark W. Randolph , Shane Charles Hollmer , Pau-Ling Chen , Richard M. Fastow
发明人： Mark W. Randolph , Shane Charles Hollmer , Pau-Ling Chen , Richard M. Fastow
IPC分类号： H01L2973
CPC分类号： H01L27/11568 , H01L27/115
摘要： An array of memory cells includes a plurality of memory cells interconnected via a grid of M wordlines and M bitlines, wherein M=2, 3, 4, 5, . . . wherein each of the M bitlines is buried. The array further includes a plurality of contacts, wherein each of the plurality of contacts is formed every N wordlines, N=1, 2, 3, . . . , wherein each of the plurality of contacts overlies a gate of a different one of the plurality of memory cells. A strap connects one of the buried bitlines to a gate that underlies one of the plurality of contacts, and wherein contacts overlying a first bit line are staggered with respect to contacts overlying a second bit line that is adjacent to the first bit line.
摘要翻译：存储器单元阵列包括通过M字线和M位线的网格互连的多个存储器单元，其中M = 2,3,4,5。。。其中埋设M个位线。该阵列还包括多个触点，其中，每N个字线N = 1,2,3，形成多个触点中的每一个。。。，其中所述多个触点中的每一个覆盖所述多个存储单元中的不同的存储单元的栅极。带子将一个掩埋位线连接到位于多个触点中的一个的栅极，并且其中覆盖第一位线的触点相对于与第一位线相邻的第二位线的触点交错。

3. 发明授权

US5844840A High voltage NMOS pass gate having supply range, area, and speed advantages 失效
标题翻译：具有供电范围，面积和速度优势的高压NMOS通道门
公开(公告)号：US5844840A
公开(公告)日：1998-12-01
申请号：US914543
申请日：1997-08-19
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
IPC分类号： G11C8/08 , G11C16/06
CPC分类号： G11C8/08
摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.
摘要翻译：根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管阈值电压实际上驱动到字线上。根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。

4. 发明授权

US09177639B1 Memory devices, circuits and methods having data values based on dynamic change in material property 有权
标题翻译：具有基于材料特性的动态变化的数据值的存储器件，电路和方法
公开(公告)号：US09177639B1
公开(公告)日：2015-11-03
申请号：US13315652
申请日：2011-12-09
申请人： John Ross Jameson , Shane Charles Hollmer , Nad Edward Gilbert
发明人： John Ross Jameson , Shane Charles Hollmer , Nad Edward Gilbert
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C11/5685 , G11C11/5614 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C27/02 , G11C2013/0054
摘要： A method can include determining a data value stored in a memory element of a memory cell array based on the length of time required to cause a property of the memory element to change. A memory device can include a plurality of elements programmable into at least two different states; and an electrical bias section that applies sense conditions to a selected element; and a sense section configured to distinguish between the two different states according to whether a change in property occurs in the selected element within a predetermined time under the sense conditions.
摘要翻译：一种方法可以包括基于使存储元件的属性改变所需的时间长度来确定存储在存储单元阵列的存储元件中的数据值。存储器件可以包括可编程成至少两个不同状态的多个元件; 以及对所选元件应用感测条件的电偏压部分; 以及感测部，被配置为根据在感测条件下的预定时间内是否在所选元素中发生属性的变化来区分两种不同状态。

5. 发明授权

US08331128B1 Reconfigurable memory arrays having programmable impedance elements and corresponding methods 有权
标题翻译：具有可编程阻抗元件和相应方法的可重构存储器阵列
公开(公告)号：US08331128B1
公开(公告)日：2012-12-11
申请号：US12629531
申请日：2009-12-02
申请人： Narbeh Derhacobian , Shane Charles Hollmer
发明人： Narbeh Derhacobian , Shane Charles Hollmer
IPC分类号： G11C11/00 , G11C17/00
CPC分类号： G11C13/0069 , G11C7/00 , G11C8/16 , G11C11/005 , G11C11/404 , G11C11/56 , G11C11/5642 , G11C13/0004 , G11C13/0011 , G11C13/0035 , G11C13/004 , G11C13/0097 , G11C14/0045 , G11C29/816
摘要： A memory device may include a plurality of memory cells each having elements with at least one solid ion conductor programmable between at least two different impedance states for at least two different data retention times, the plurality of memory cells being dividable into a plurality of portions, each portion being separately configurable for one of the data retention times.
摘要翻译：存储器件可以包括多个存储器单元，每个存储单元具有至少一个固体离子导体的元件，所述固体离子导体可在至少两个不同的阻抗状态之间编程用于至少两个不同的数据保持时间，所述多个存储器单元可分为多个部分，每个部分可以单独配置用于数据保留时间之一。

6. 发明授权

US6141244A Multi level sensing of NAND memory cells by external bias current 有权
标题翻译：通过外部偏置电流对NAND存储单元的多电平感测
公开(公告)号：US6141244A
公开(公告)日：2000-10-31
申请号：US388696
申请日：1999-09-02
申请人： Joseph G. Pawletko , Pau-Ling Chen , Shane Charles Hollmer
发明人： Joseph G. Pawletko , Pau-Ling Chen , Shane Charles Hollmer
IPC分类号： G11C11/56 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5642 , G11C2211/5642
摘要： A method and circuit for sensing multi states of a NAND memory cell by applying plurality of external sensing bias current at a constant positive gate and bias voltage and detecting a cell current wherein the cell current depends upon the state of the memory cell.
摘要翻译：一种用于通过以恒定正栅极和偏置电压施加多个外部感测偏置电流来感测NAND存储器单元的多状态并检测单元电流的方法和电路，其中单元电流取决于存储单元的状态。

7. 发明授权

US09721658B1 Memory devices and methods for storing single data value in multiple programmable resistance elements 有权
公开(公告)号：US09721658B1
公开(公告)日：2017-08-01
申请号：US14791416
申请日：2015-07-04
申请人： Shane Charles Hollmer , Nad Edward Gilbert
发明人： Shane Charles Hollmer , Nad Edward Gilbert
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/004 , G11C7/04 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/0061 , G11C13/0069 , G11C2013/0066 , G11C2013/0073 , G11C2013/0078 , G11C2213/79
摘要： A memory device can include a plurality of bit lines; plurality of memory elements coupled to the bit lines, each memory element including a memory layer formed between two electrodes, the memory layer being programmable between a plurality of different resistance states by creation and removal of conductive regions therein by application of electric fields; and at least one sense amplifier (SA) configured to compare a first value, corresponding to a resistance state of a first memory element, to a second value, corresponding to a resistance state of a second memory element.

8. 发明授权

US08687403B1 Circuits having programmable impedance elements 有权
标题翻译：具有可编程阻抗元件的电路
公开(公告)号：US08687403B1
公开(公告)日：2014-04-01
申请号：US13157713
申请日：2011-06-10
申请人： Narbeh Derhacobian , Shane Charles Hollmer , Ishai Naveh
发明人： Narbeh Derhacobian , Shane Charles Hollmer , Ishai Naveh
IPC分类号： G11C11/00
CPC分类号： H01L45/085 , G11C11/005 , G11C13/0007 , G11C13/0011 , G11C14/0045 , G11C14/009
摘要： An integrated circuit (IC) device may include a first portion having a plurality of volatile memory cells; and a second portion coupled by a data transfer path to the first portion, the second portion including a plurality of nonvolatile memory cells, each nonvolatile memory cell including at least one resistive element programmable more than once between different resistance values. A memory device may also include variable impedance elements accessible by access bipolar junction transistors (BJTs) having at least a portion formed by a semiconductor layer formed over a substrate. A memory device may also include a plurality of memory elements that each includes a dielectric layer formed between a first and second electrode, the dielectric layer including a solid electrolyte with a soluble metal having a mobility less than that of silver in a germanium disulfide.
摘要翻译：集成电路（IC）装置可以包括具有多个易失性存储器单元的第一部分; 以及第二部分，其通过数据传输路径耦合到所述第一部分，所述第二部分包括多个非易失性存储器单元，每个非易失性存储单元包括在不同电阻值之间不止一次可编程的至少一个电阻元件。存储器件还可以包括可由存取双极结型晶体管（BJT）访问的可变阻抗元件，其中至少一部分由形成在衬底上的半导体层形成。存储器件还可以包括多个存储器元件，每个存储器元件包括形成在第一和第二电极之间的电介质层，该电介质层包括具有小于二硫化锗中银的迁移率的可溶性金属的固体电解质。

9. 发明授权

US08654561B1 Read methods, circuits and systems for memory devices 有权
标题翻译：读取存储器件的方法，电路和系统
公开(公告)号：US08654561B1
公开(公告)日：2014-02-18
申请号：US13276763
申请日：2011-10-19
申请人： John Ross Jameson , John Dinh , Derric Lewis , Daniel Wang , Shane Charles Hollmer , Nad Edward Gilbert , Janet Wang
发明人： John Ross Jameson , John Dinh , Derric Lewis , Daniel Wang , Shane Charles Hollmer , Nad Edward Gilbert , Janet Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/1673 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C13/0061
摘要： A memory device can include a plurality of programmable elements; at least one sense circuit that generates sense data values from detected impedances of accessed programmable elements; and at least one data store circuit that stores initial data values from the at least one sense circuit, and stores output data values from the at least one sense circuit after check conditions have been applied to at least one programmable element. The check conditions can induce a change in impedance for programmable elements programmed to at least one predetermined state. Methods can include reading data from at least one memory cell of a memory device comprising a plurality of such memory cells; if the read data has a first value, providing such data as an output value; and if the read data has a second value, repeating access to the memory cell to confirm the read data value.
摘要翻译：存储器件可以包括多个可编程元件; 至少一个感测电路，其从所访问的可编程元件的检测到的阻抗产生感测数据值; 以及至少一个数据存储电路，其存储来自所述至少一个感测电路的初始数据值，并且在检查条件已应用于至少一个可编程元件之后存储来自所述至少一个感测电路的输出数据值。检查条件可以引起编程为至少一个预定状态的可编程元件的阻抗变化。方法可以包括从包括多个这样的存储器单元的存储器件的至少一个存储器单元读取数据; 如果读取的数据具有第一值，则提供这样的数据作为输出值; 并且如果读取的数据具有第二值，则重复访问存储器单元以确认读取的数据值。

10. 发明授权

US08274842B1 Variable impedance memory device having simultaneous program and erase, and corresponding methods and circuits 有权
标题翻译：具有同时编程和擦除的可变阻抗存储器件，以及相应的方法和电路
公开(公告)号：US08274842B1
公开(公告)日：2012-09-25
申请号：US12566790
申请日：2009-09-25
申请人： Shane Charles Hollmer , Nad Edward Gilbert , John Dinh
发明人： Shane Charles Hollmer , Nad Edward Gilbert , John Dinh
IPC分类号： G11C7/10
CPC分类号： G11C13/0011 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2213/79
摘要： An integrated circuit may include: access circuits that couple first electrodes of a plurality of programmable metallization cells (PMC) to access paths in parallel, each PMC comprising a solid ion conducting material formed between the first electrode and a second electrode; a plurality of write circuits, each coupled to a different access path, and each coupling the corresponding access path to a first voltage in response to input write data having a first value and to a second voltage in response to the input write data having a second value; and a node setting circuit that maintains second electrodes of the PMCs at a substantially constant third voltage while write circuits couple the access paths to the first or second voltages.
摘要翻译：集成电路可以包括：将多个可编程金属化单元（PMC）的第一电极并联的访问路径的访问电路，每个PMC包括形成在第一电极和第二电极之间的固体离子传导材料; 多个写入电路，每个写入电路耦合到不同的访问路径，并且响应于具有第一值的输入写入数据和响应于输入的写入数据具有第二电压而将对应的访问路径耦合到第一电压到第二电压值; 以及节点设置电路，其将PMC的第二电极保持在基本上恒定的第三电压，同时写电路将访问路径耦合到第一或第二电压。

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