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1. 发明授权

US06438030B1 Non-volatile memory, method of manufacture, and method of programming 有权
标题翻译：非易失性存储器，制造方法和编程方法
公开(公告)号：US06438030B1
公开(公告)日：2002-08-20
申请号：US09639195
申请日：2000-08-15
申请人： Chung-You Hu , Kuo-Tung Chang , Wei-Hua Liu , David Burnett
发明人： Chung-You Hu , Kuo-Tung Chang , Wei-Hua Liu , David Burnett
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/10 , H01L27/115
摘要： A semiconductor device includes a non-volatile memory, such as an electrically erasable programmable read only memory (EEPROM) array of memory cells. The memory is arranged as an array of cells in rows and columns. P-well regions of the array are spaced apart and electrically isolated by shallow trench features. The cells of each column are positioned within a respective isolated p-well region. Control gates of sequentially corresponding memory cells in columns of the array are electrically coupled by common wordlines. Bitlines electrically couple drain regions of each memory cell in the respective columns of the memory cell array. Source lines electrically couple source regions of each memory cell in the respective columns of the array. The source lines and at least one memory cell in each column of the array are electrically coupled to the p-well region corresponding to the column of the source line and cell. Each column of the array is therefore located within an isolated well, common to the cells in the column but isolated from other wells of other columns. The array is programmed by pulsing potentials as to each column, with isolation of results for each column.
摘要翻译：半导体器件包括诸如存储器单元的电可擦除可编程只读存储器（EEPROM）阵列的非易失性存储器。内存被排列成行和列中的单元格数组。阵列的P阱区域被间隔开并且通过浅沟槽特征电隔离。每个柱的细胞位于相应的分离的p阱区内。阵列列中顺序对应的存储单元的控制栅极通过通用字线电耦合。位线电耦合存储器单元阵列的相应列中的每个存储器单元的漏极区域。源极线将阵列的相应列中的每个存储单元的源极区域电耦合。阵列的每列中的源极线和至少一个存储单元电耦合到对应于源极线和单元的列的p阱区。因此，阵列的每列都位于隔离阱中，与柱中的单元通用，但与其他列的其他孔隔离。通过脉冲每个列的电位编程阵列，隔离每列的结果。

2. 发明授权

US08455268B2 Gate replacement with top oxide regrowth for the top oxide improvement 有权
标题翻译：门顶置换，顶部氧化物再生长，用于顶部氧化物改良
公开(公告)号：US08455268B2
公开(公告)日：2013-06-04
申请号：US11848515
申请日：2007-08-31
申请人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
发明人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
IPC分类号： H01L21/00 , H01L21/311
CPC分类号： H01L29/7923 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
摘要翻译：提供了替换/重整存储单元的电荷存储元件周围的顶部氧化物的方法和提高存储单元的电荷存储元件周围的顶部氧化物的质量的方法。该方法可以包括从存储器单元去除第一顶部氧化物上的第一多晶硅; 从存储器单元中去除第一顶部氧化物; 以及在所述电荷存储元件周围形成第二顶部氧化物。可以通过氧化电荷存储元件的一部分或通过在电荷存储元件上形成牺牲层并将牺牲层氧化成第二顶部氧化物来形成第二顶部氧化物。

3. 发明授权

US08329598B2 Sacrificial nitride and gate replacement 有权
标题翻译：牺牲氮化物和栅极替代
公开(公告)号：US08329598B2
公开(公告)日：2012-12-11
申请号：US13153558
申请日：2011-06-06
申请人： Chungho Lee , Kuo-Tung Chang , Hiroyuki Kinoshita , Huaqiang Wu , Fred Cheung
发明人： Chungho Lee , Kuo-Tung Chang , Hiroyuki Kinoshita , Huaqiang Wu , Fred Cheung
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/28282 , H01L21/3185 , H01L27/115 , H01L27/11568 , H01L29/42348 , H01L29/7923
摘要： Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.
摘要翻译：提供了在存储单元的电荷存储材料层周围形成顶部氧化物的方法以及提高存储单元的电荷存储材料层周围的顶部氧化物的质量的方法。该方法可以包括在半导体衬底上提供电荷存储层，电荷存储层上的氮化物层和氮化物层上的第一多晶硅层，并将氮化物层的至少一部分转化为顶部氧化物。通过将氮化物层的至少一部分转化为顶部氧化物层，可以提高所得顶部氧化物层的质量。

4. 发明授权

US08319266B1 Etch stop layer for memory cell reliability improvement 有权
标题翻译：蚀刻停止层，提高记忆体的可靠性
公开(公告)号：US08319266B1
公开(公告)日：2012-11-27
申请号：US11008240
申请日：2004-12-10
申请人： Hiroyuki Kinoshita , Angela Hui , Hsiao-Han Thio , Kuo-Tung Chang , Minh Van Ngo , Hiroyuki Ogawa
发明人： Hiroyuki Kinoshita , Angela Hui , Hsiao-Han Thio , Kuo-Tung Chang , Minh Van Ngo , Hiroyuki Ogawa
IPC分类号： H01L29/788
CPC分类号： H01L21/0217 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.
摘要翻译：提供存储器件和制造存储器件的方法。在基板上形成第一电介质层，在第一电介质层上形成浮栅，在浮栅上形成第二电介质层，在第二电介质层上形成控制栅，还包括至少一层，保形膜形成在存储器件的表面上。

5. 发明授权

US08144522B2 Erasing flash memory using adaptive drain and/or gate bias 有权
标题翻译：使用自适应漏极和/或栅极偏置擦除闪存
公开(公告)号：US08144522B2
公开(公告)日：2012-03-27
申请号：US12831085
申请日：2010-07-06
申请人： Kuo-Tung Chang , Wei Zheng
发明人： Kuo-Tung Chang , Wei Zheng
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/04 , G11C16/3468 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50004
摘要： A hot hole erase operation as described herein can be utilized for a flash memory device having an array of memory cells. The erase operation employs an adaptive erase bias voltage scheme where the drain bias voltage (and/or the gate bias voltage) is dynamically adjusted in response to an erase pulse count corresponding to a preliminary erase operation during which a relatively small portion of a sector is erased. The adjustment of the erase bias voltage in this manner enables the rest of the sector to be erased using erase bias voltages that are better suited to the current erase characteristics of the sector.
摘要翻译：如本文所述的热孔擦除操作可以用于具有存储器单元阵列的闪存器件。擦除操作采用自适应擦除偏置电压方案，其中响应于与初步擦除操作相对应的擦除脉冲计数来动态地调节漏极偏置电压（和/或栅极偏置电压），在该擦除脉冲计数期间相对较小部分的扇区是擦除以这种方式调整擦除偏置电压使得能够使用更适合于扇区的当前擦除特性的擦除偏置电压来擦除扇区的其余部分。

6. 发明授权

US07952938B2 Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory 有权
标题翻译：选择性地应用字线偏置，以最大限度地减少非易失性存储器擦除期间电磁场中的边缘效应
公开(公告)号：US07952938B2
公开(公告)日：2011-05-31
申请号：US12773232
申请日：2010-05-04
申请人： Gulzar Ahmed Kathawala , Wei Zheng , Zhizheng Liu , Sung-Yong Chung , Timothy Thurgate , Kuo-Tung Chang , Sheung-Hee Park , Gabrielle Wing Han Leung
发明人： Gulzar Ahmed Kathawala , Wei Zheng , Zhizheng Liu , Sung-Yong Chung , Timothy Thurgate , Kuo-Tung Chang , Sheung-Hee Park , Gabrielle Wing Han Leung
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.
摘要翻译：提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元当存储器单元是端行存储单元时。优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应在擦除期间应用于细胞。

7. 发明授权

US07915123B1 Dual charge storage node memory device and methods for fabricating such device 有权
标题翻译：双电荷存储节点存储器件及其制造方法
公开(公告)号：US07915123B1
公开(公告)日：2011-03-29
申请号：US11408866
申请日：2006-04-20
申请人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Kyunghoon Min , Chi Chang
发明人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Amol Joshi , Kyunghoon Min , Chi Chang
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/792 , Y10S438/954
摘要： A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.
摘要翻译：提供了一种双节点存储器件及其制造方法。在一个实施例中，该方法包括在半导体衬底上形成具有绝缘体层，电荷存储层，缓冲层和牺牲层的分层结构。这些层被图案化以形成两个间隔开的堆叠和在堆叠之间的暴露的衬底部分。在暴露的基板上形成栅极绝缘体和栅电极，去除牺牲层和缓冲层。沉积覆盖电荷存储层的另外的绝缘体层，以在栅电极的每一侧上形成绝缘体存储层 - 绝缘体存储器存储区域。侧壁间隔件形成在覆盖存储区域的栅电极的侧壁上。在与栅极间隔开的衬底中形成位线，并且形成与栅电极和侧壁间隔物接触的字线。

8. 发明授权

US07659569B2 Work function engineering for FN erase of a memory device with multiple charge storage elements in an undercut region 有权
标题翻译：用于在擦除区域中具有多个电荷存储元件的存储器件的FN擦除的功能工程功能
公开(公告)号：US07659569B2
公开(公告)日：2010-02-09
申请号：US11953690
申请日：2007-12-10
申请人： Wei Zheng , Kuo-Tung Chang , Sung-Yong Chung , Ashot Melik-Martirosian
发明人： Wei Zheng , Kuo-Tung Chang , Sung-Yong Chung , Ashot Melik-Martirosian
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/28273 , G11C16/0441 , G11C16/0491 , H01L29/42324 , H01L29/7781 , H01L29/7883
摘要： A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function material, such as P+ polycrystalline silicon or a P-type metal, and/or a high-K material. The memory cell can reduce the likelihood of gate electron injection through the gate electrode and into the charge storage elements during a Fowler-Nordheim erase by employing such tunneling barrier. Systems and methods of fabricating memory devices having at least one such memory cell are provided.
摘要翻译：一种由多个存储单元组成的存储器件，每个存储器单元可以分别包括形成在隧道势垒之下并与每个存储单元的栅极氧化层相邻的底切区域中的多个电荷存储元件。隧道势垒可以由诸如P +多晶硅或P型金属的高功函材料和/或高K材料形成。通过采用这种隧道势垒，存储器单元可以降低在Fowler-Nordheim擦除期间栅极电子注入通过栅电极并进入电荷存储元件的可能性。提供了制造具有至少一个这样的存储单元的存储器件的系统和方法。

9. 发明授权

US07622389B1 Selective contact formation using masking and resist patterning techniques 有权
标题翻译：使用掩模和抗蚀剂图案化技术的选择性接触形成
公开(公告)号：US07622389B1
公开(公告)日：2009-11-24
申请号：US11411353
申请日：2006-04-25
申请人： Kyunghoon Min , Mark Chang , Ning Cheng , Brian Osborn , Kevin Song , Fei Wang , Angela Hui , Hiroyuki Kinoshita , Kuo-Tung Chang
发明人： Kyunghoon Min , Mark Chang , Ning Cheng , Brian Osborn , Kevin Song , Fei Wang , Angela Hui , Hiroyuki Kinoshita , Kuo-Tung Chang
IPC分类号： H01L21/302
CPC分类号： H01L27/11526 , H01L27/11548
摘要： A method for manufacturing a semiconductor device including selective conductive contacts includes the step of depositing a resist over first and second memory device components, each of the first and second components comprising junctions formed in the substrate and a gate formed on the substrate between the junctions. The resist is then removed from the second components to thereby form a resist opening above each of the second component control gates and junctions. The resist is then etched to thereby expose each of the first component control gates but not the substrate surrounding the first component control gates. Conductive contacts are then formed on the exposed first component control gates, and the second component control gates and junctions.
摘要翻译：包括选择性导电触点的半导体器件的制造方法包括在第一和第二存储器件部件上沉积抗蚀剂的步骤，第一和第二部件中的每一个包括形成在衬底中的接合部以及在接合部之间形成在衬底上的栅极。然后将抗蚀剂从第二部件移除，从而在每个第二部件控制浇口和结上形成抗蚀剂开口。然后蚀刻抗蚀剂，从而暴露第一组分控制栅极中的每一个，而不暴露围绕第一组分控制栅极的衬底。然后在暴露的第一部件控制栅极和第二部件控制栅极和结上形成导电触点。

10. 发明授权

US07599228B1 Flash memory device having increased over-erase correction efficiency and robustness against device variations 有权
标题翻译：闪存器件具有增加的过擦除校正效率和针对器件变化的鲁棒性
公开(公告)号：US07599228B1
公开(公告)日：2009-10-06
申请号：US10976760
申请日：2004-11-01
申请人： Qiang Lu , Kuo-Tung Chang , Kazuhiro Mizutani , Sung-Chul Lee , Sheung-Hee Park , Ming-Sang Kwan
发明人： Qiang Lu , Kuo-Tung Chang , Kazuhiro Mizutani , Sung-Chul Lee , Sheung-Hee Park , Ming-Sang Kwan
IPC分类号： G11C16/04
CPC分类号： G11C16/3404
摘要： A memory device is provided including circuitry for correcting an over-erased memory cell in the memory device. The memory device may include a substrate. A control gate and a floating gate may be formed over the substrate. The memory device may include a source region and a drain region. A first resistive element may be coupled between the source region and the control gate.
摘要翻译：提供了一种存储器件，其包括用于校正存储器件中的擦除过的存储器单元的电路。存储器件可以包括衬底。可以在衬底上形成控制栅极和浮置栅极。存储器件可以包括源极区域和漏极区域。第一电阻元件可以耦合在源极区域和控制栅极之间。

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