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1. 发明授权

US06266275B1 Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for nand array flash memory 有权
标题翻译：双源多晶硅选择门结构和编程方法，利用单隧道氧化物进行阵列闪存存储
公开(公告)号：US06266275B1
公开(公告)日：2001-07-24
申请号：US09410512
申请日：1999-09-30
申请人： Paul-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
发明人： Paul-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
IPC分类号： G11C700
CPC分类号： G11C16/0483
摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
摘要翻译：串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。串联选择晶体管连接到NAND串中的最后一个晶体管。源选择晶体管连接到阵列Vss电源。为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

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