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1. 发明授权

US06847913B2 Ambulatory surface skin temperature monitor 有权
标题翻译：动态表面皮肤温度监测仪
公开(公告)号：US06847913B2
公开(公告)日：2005-01-25
申请号：US10264442
申请日：2002-10-04
申请人： Fredrick M. Wigley , Robert A. Wise , Paul D. Schwartz , Ark L. Lew , David D. Scott , Binh Q. Le
发明人： Fredrick M. Wigley , Robert A. Wise , Paul D. Schwartz , Ark L. Lew , David D. Scott , Binh Q. Le
IPC分类号： A61B5/00 , A61B5/053 , A61B5/103 , G01K13/00
CPC分类号： G01K13/002 , A61B5/0008 , A61B5/01 , A61B5/0531 , A61B5/441 , A61B5/6843 , A61B2560/0242 , A61B2560/0412 , G06F19/00
摘要： An ambulatory skin temperature monitoring system. A flexible band is attachable to a patient. The flexible band also secures an electronics assembly that comprises the various electrical components that monitor and operate the ambulatory skin temperature monitoring system. At least one skin temperature sensor is positioned so that it is in contact with the patients skin when the system is attached to the patient. There is also an ambient temperature sensor positioned on the top surface of the electronics assembly housing for measuring and contrasting the ambient temperature to the skin temperature. The electronics assembly positioned within generally comprises a power source and a micro-controller. The micro-controller is coupled with the skin temperature sensor and the ambient temperature sensor. The micro-controller also includes a memory unit for storing temperature data obtained from the skin temperature sensor and the ambient temperature sensor. Data from the system can be downloaded to a remote computing device where software can plot the data in a desired format for analysis by medical personnel.
摘要翻译：门诊皮肤温度监测系统。柔性带可附着于患者。柔性带还固定电子组件，其包括监测和操作动态皮肤温度监测系统的各种电气部件。定位至少一个皮肤温度传感器，使得当系统附接到患者时，它与患者皮肤接触。还有一个环境温度传感器位于电子组件外壳的顶表面上，用于测量和对比环境温度与皮肤温度。定位在其中的电子组件通常包括电源和微控制器。微控制器与皮肤温度传感器和环境温度传感器耦合。微控制器还包括用于存储从皮肤温度传感器和环境温度传感器获得的温度数据的存储单元。来自系统的数据可以下载到远程计算设备，其中软件可以以期望的格式绘制数据，以供医务人员分析。

2. 发明授权

US06768679B1 Selection circuit for accurate memory read operations 有权
标题翻译：选择电路，用于精确的存储器读操作
公开(公告)号：US06768679B1
公开(公告)日：2004-07-27
申请号：US10361378
申请日：2003-02-10
申请人： Binh Q. Le , Michael Achter , Lee Cleveland , Pauling Chen
发明人： Binh Q. Le , Michael Achter , Lee Cleveland , Pauling Chen
IPC分类号： G11C1606
CPC分类号： G11C16/0491 , G11C16/24 , G11C16/26
摘要： A selection circuit for sensing current in a target cell during a memory read operation is disclosed. According to one embodiment, the selection circuit comprises a sensing circuit selector connected to a sensing circuit and a ground selector connected to ground. The ground selector connects a first bit line of the target cell to ground, and the sensing circuit selector connects a second bit line of the target cell to the sensing circuit. The sensing circuit selector also connects a third bit line of a first neighboring cell to the sensing circuit. The first neighboring cell shares the second bit line with the target cell.
摘要翻译：公开了一种用于在存储器读取操作期间感测目标单元中的电流的选择电路。根据一个实施例，选择电路包括连接到感测电路的感测电路选择器和连接到地的接地选择器。接地选择器将目标单元的第一位线连接到地，并且感测电路选择器将目标单元的第二位线连接到感测电路。感测电路选择器还将第一相邻单元的第三位线连接到感测电路。第一相邻单元与目标单元共享第二位线。

3. 发明授权

US06768677B2 Cascode amplifier circuit for producing a fast, stable and accurate bit line voltage 有权
公开(公告)号：US06768677B2
公开(公告)日：2004-07-27
申请号：US10302672
申请日：2002-11-22
申请人： Binh Q. Le , Lee Cleveland , Pauling Chen
发明人： Binh Q. Le , Lee Cleveland , Pauling Chen
IPC分类号： G11C1606
CPC分类号： G11C16/24 , G11C7/067
摘要： A cascode amplifier circuit which generates a fast, stable and accurate bit line voltage is disclosed. According to one exemplary embodiment, the cascode amplifier circuit comprises a transistor having a source connected to a bit line voltage and a drain connected to an output voltage. The cascode amplifier circuit also comprises a differential circuit having an inverting input connected to the bit line voltage, a non-inverting input connected to a reference voltage, and an output connected to a gate of the first transistor. The operation of the transistor and the differential circuit generate a fast, stable the accurate bit line voltage.

4. 发明授权

US06535424B2 Voltage boost circuit using supply voltage detection to compensate for supply voltage variations in read mode voltage 有权
标题翻译：电压升压电路使用电源电压检测来补偿读取模式电压中的电源电压变化
公开(公告)号：US06535424B2
公开(公告)日：2003-03-18
申请号：US09915018
申请日：2001-07-25
申请人： Binh Q. Le , Masaru Yano , Santosh K. Yachareni
发明人： Binh Q. Le , Masaru Yano , Santosh K. Yachareni
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C8/08
摘要： Flash memory array systems and methods are disclosed for producing a supply regulated boost voltage, wherein the application of a supply voltage to a supply voltage level detection circuit (e.g., analog to digital converter, digital thermometer) which is used to generating one or more supply voltage level detection signals from measurement of the supply voltage level applied to the voltage boost circuit, which may be used as a boosted wordline voltage for the read mode operations of programmed memory cells, and wherein the supply voltage level detection signals are applied to a boosted voltage compensation circuit to generate one or more boosted voltage compensation signals which are applied to a voltage boost circuit operable to generate a regulated boosted voltage for a flash memory array of programmed core cells. Thus, a fast compensation means is disclosed for the VCC power supply variations typically reflected in the output of the boost voltage circuit supplied to the word line of the flash memory array, thereby generating wordline voltages during the read mode which are substantially independent of variations in the supply voltage.
摘要翻译：闪存阵列系统和方法被公开用于产生电源调节升压电压，其中将电源电压施加到用于产生一个或多个电源的电源电压电平检测电路（例如，模数转换器，数字温度计）电压电平检测信号来自测量施加到升压电路的电源电压电平，其可以用作用于编程存储器单元的读取模式操作的升压字线电压，并且其中电源电压电平检测信号被施加到升压电压补偿电路以产生一个或多个升压电压补偿信号，所述升压电压补偿信号被施加到升压电路，所述升压电路可操作以产生用于编程核心单元的闪存阵列的调节升压电压。因此，公开了一种快速补偿装置，用于通常反映在提供给闪速存储器阵列的字线的升压电压电路的输出中的VCC电源变化，从而在读取模式期间产生字线电压，其基本上与电源电压。

5. 发明授权

US06510082B1 Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold 有权
标题翻译：具有相邻位充电和保持的虚拟接地闪速EPROM阵列的漏极检测方案
公开(公告)号：US06510082B1
公开(公告)日：2003-01-21
申请号：US09999869
申请日：2001-10-23
申请人： Binh Q. Le , Pau-Ling Chen , Michael A. Van Buskirk , Santosh K. Yachareni , Michael S. C. Chung , Kazuhiro Kurihara , Shane Hollmer
发明人： Binh Q. Le , Pau-Ling Chen , Michael A. Van Buskirk , Santosh K. Yachareni , Michael S. C. Chung , Kazuhiro Kurihara , Shane Hollmer
IPC分类号： G11C1604
CPC分类号： G11C16/0491 , G11C16/28
摘要： A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e.g., about 1.2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e.g., about 1.2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a drain terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.
摘要翻译：公开了一种用于产生用于虚拟接地闪速存储器操作的闪存单元的逻辑状态的指示的系统。该系统包括位线充电和保持电路，其可操作以将读取感测电压（例如，约1.2伏特）施加到与所感测的电池相邻的闪光阵列的单元的漏极端子相关联的位线，其中所施加的漏极端子电压基本上与施加到要被感测的所选择的存储器单元的漏极端子位线的单元检测电压（例如，约1.2伏特）相同。该系统还包括选择性位线解码电路，其可操作以选择要感测的存储器单元的位线和相邻单元的位线;以及核心单元感测电路，其可操作以感测核心单元感测电流在与存储器读取操作期间被感测的所选择的存储器单元的漏极端子相关联的位线处，并产生闪存单元逻辑状态的指示，其基本上与相邻单元的电荷共享泄漏电流无关。

6. 发明授权

US6009014A Erase verify scheme for NAND flash 失效
标题翻译：擦除NAND闪存的验证方案
公开(公告)号：US6009014A
公开(公告)日：1999-12-28
申请号：US90296
申请日：1998-06-03
申请人： Shane C. Hollmer , Chung-You Hu , Binh Q. Le , Pau-ling Chen , Jonathan Su , Ravi Gutala , Colin Bill
发明人： Shane C. Hollmer , Chung-You Hu , Binh Q. Le , Pau-ling Chen , Jonathan Su , Ravi Gutala , Colin Bill
IPC分类号： G11C16/04 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/344
摘要： The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.
摘要翻译：本发明提供了一种验证NAND串中的所有闪存EEPROM晶体管是否被适当地擦除，而不会通过向NAND阵列的底部选择栅极的源施加偏置电压而对其进行过载并向非线性擦除验证电压施加非负的擦除验证电压在擦除验证期间每个晶体管的控制栅极。偏置电压至少等于最坏情况晶体管的擦除阈值电压，以确保正确的擦除验证。如果所有晶体管都不被擦除，则执行另一个擦除操作。重复擦除直到擦除验证操作指示所有晶体管被正确擦除。通过根据本发明的擦除和验证，NAND阵列被完全和适当地擦除，同时使阵列过度减少。

7. 发明授权

US06881593B2 Semiconductor die adapter and method of using 有权
标题翻译：半导体晶片适配器及其使用方法
公开(公告)号：US06881593B2
公开(公告)日：2005-04-19
申请号：US10159682
申请日：2002-05-31
申请人： Binh Q. Le , Ark L. Lew , Harry K. Charles, Jr. , Paul D. Schwartz , Seppo J. Lehtonen , Sharon X. Ling
发明人： Binh Q. Le , Ark L. Lew , Harry K. Charles, Jr. , Paul D. Schwartz , Seppo J. Lehtonen , Sharon X. Ling
IPC分类号： G01R1/04 , G01R31/28 , H01L23/498 , H01L21/66
CPC分类号： H01L23/49827 , G01R1/0416 , G01R31/2884 , H01L24/48 , H01L24/49 , H01L2224/05624 , H01L2224/05644 , H01L2224/32145 , H01L2224/45099 , H01L2224/4826 , H01L2224/48464 , H01L2224/48471 , H01L2224/49109 , H01L2224/73215 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01079 , H01L2924/07811 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor die adapter assembly includes a semiconductor die cut from a wafer, the die having an active surface including bond pads. A die adapter, also having bond pads, is bonded to the semiconductor die. Die-to-adapter connectors electrically connect the die bond pads to the adapter bond pads. Finally, adapter-to-substrate connectors electrically connect the adapter bond pads to a device substrate. Having bond pads on the die adapter eliminates the need to break and remake the electrical connections to the original bond pads on the die during burn-in testing of the die.
摘要翻译：半导体管芯适配器组件包括从晶片切割的半导体管芯，该管芯具有包括接合焊盘的活性表面。还具有接合焊盘的芯片适配器被结合到半导体管芯。管芯到适配器连接器将管芯接合焊盘电连接到适配器接合焊盘。最后，适配器到基板连接器将适配器接合焊盘电连接到器件衬底。在裸片适配器上具有接合垫消除了在裸片的老化测试期间破坏并重新制造与芯片上的原始接合焊盘的电连接的需要。

8. 发明授权

US06493266B1 Soft program and soft program verify of the core cells in flash memory array 有权
标题翻译：软件程序和软件程序验证闪存阵列中的核心单元
公开(公告)号：US06493266B1
公开(公告)日：2002-12-10
申请号：US09829193
申请日：2001-04-09
申请人： Santosh K. Yachareni , Darlene G. Hamilton , Binh Q. Le , Kazuhiro Kurihara
发明人： Santosh K. Yachareni , Darlene G. Hamilton , Binh Q. Le , Kazuhiro Kurihara
IPC分类号： G11C1134
CPC分类号： G11C16/3409 , G11C16/0475 , G11C16/3404 , G11C16/3436
摘要： A method and system are disclosed for memory cell soft program and soft program verify, to adjust, or correct the threshold voltage between a target minimum and maximum, which may be employed in association with a dual bit memory cell architecture. The method includes applying one reference voltage signal to the over erased core cell, and a different reference voltage signal to the reference cell, comparing the two currents produced by each, selectively verifying proper soft programming of one or more bits of the cell, determining that the dual bit memory cell is properly soft programmed. The method may also comprise selectively re-verifying proper soft programming of the cells after selectively soft programming at least one or more bits of the cell.
摘要翻译：公开了用于存储器单元软程序和软程序验证，调整或校正目标最小值与最大值之间的阈值电压的方法和系统，其可以与双位存储器单元架构相关联使用。该方法包括将一个参考电压信号施加到过擦除的核心单元，以及将不同的参考电压信号施加到参考单元，比较由每个产生的两个电流，选择性地验证单元的一个或多个位的适当的软编程，确定双位存储单元被正确软编程。该方法还可以包括在对该小区的至少一个或多个比特进行选择性软编程之后，选择性地重新验证小区的适当的软编程。

9. 发明授权

US6081455A EEPROM decoder block having a p-well coupled to a charge pump for charging the p-well and method of programming with the EEPROM decoder block 有权
标题翻译： EEPROM解码器块具有耦合到用于对p阱充电的电荷泵的p阱以及用EEPROM解码器块进行编程的方法
公开(公告)号：US6081455A
公开(公告)日：2000-06-27
申请号：US232023
申请日：1999-01-14
申请人： Binh Q. Le , Pau-ling Chen , Shane C. Hollmer
发明人： Binh Q. Le , Pau-ling Chen , Shane C. Hollmer
IPC分类号： G11C8/12 , G11C16/08 , G11C16/12 , G11C16/00
CPC分类号： G11C8/12 , G11C16/08 , G11C16/12
摘要： A block decoder includes a p-well. A low voltage source is coupled to the p-well for asserting a body bias voltage to the p-well. An n-type word line pass transistor is positioned within the p-well and is coupled to a word line for passing programming voltages to the word line. A high voltage source is coupled to pass circuitry configured to assert a voltage on a gate of the pass transistor. The low voltage source is configured to apply a voltage of approximately 10 volts or more to the p-well during programming, thus reducing the voltage between the source and body region (and thus the threshold voltage as well) of NMOS transistors disposed within the p-well. Therefore, the amount of voltage needed to be applied to the pass transistors is reduced. Furthermore, the pass circuitry can work for lower supply voltages since the supply voltage is limited by the threshold voltage of the n-type transistors within the p-well.
摘要翻译：块解码器包括p阱。低电压源耦合到p阱，用于断定对p阱的体偏置电压。 n型字线传输晶体管位于p阱内并耦合到字线，用于将编程电压传递到字线。耦合高电压源以通过配置成断定传输晶体管的栅极上的电压的电路。低电压源被配置为在编程期间向p阱施加大约10伏特或更高的电压，从而降低位于p内的NMOS晶体管的源极和体区之间的电压（以及阈值电压） -好。因此，需要施加到传输晶体管的电压量减小。此外，通过电路可以用于较低的电源电压，因为电源电压受p阱内n型晶体管的阈值电压的限制。

10. 发明授权

US5644207A Integrated power source 失效
标题翻译：集成电源与所有聚合物可再充电电池分层，太阳能电池，充电器，充电控制和指示灯
公开(公告)号：US5644207A
公开(公告)日：1997-07-01
申请号：US632969
申请日：1996-04-16
申请人： Ark L. Lew , Joseph J. Suter , Binh Q. Le
发明人： Ark L. Lew , Joseph J. Suter , Binh Q. Le
IPC分类号： B60K1/04 , B60K16/00 , H01M2/10 , H01M6/50 , H01M10/42 , H01M10/46 , H02J7/02 , H02J7/35 , H02J7/00
CPC分类号： H01M10/4257 , B60K1/04 , B60K16/00 , H01M10/46 , H01M10/465 , H01M2/1022 , H01M2/1066 , H01M2/1083 , H02J7/025 , H02J7/355 , H01M6/5044 , Y02B10/14 , Y02T10/90 , Y10T307/50
摘要： A self-contained, small, lightweight, portable, renewable, modular integrated power source. The power source consists of solar cells that are laminated onto a solid state polymer battery which in turn is laminated onto a substrate containing circuits which manage the polymer battery charging. Charging of the battery can occur via solar energy or, alternatively, via RF coupling using external RF charging equipment or a hand held generator. For added support, the integrated power source is then bonded to an applications housing or structure. This integrated power source can independently power the electronic application. It can also serve as casing or housing by taking the shape of the application enclosure.
摘要翻译：独立，小巧，轻便，便携，可再生，模块化的集成电源。电源由层叠在固体聚合物电池上的太阳能电池组成，而固体聚合物电池又被层压到含有管理聚合物电池充电的电路的基板上。电池的充电可以通过太阳能或者通过使用外部RF充电设备或手持式发电机的RF耦合进行。为了增加支持，集成电源然后被结合到应用外壳或结构。该集成电源可以独立为电子应用提供电源。它还可以通过采取应用程序外壳的形状作为外壳或外壳。

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