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1. 发明授权

US4857769A Threshold voltage fluctuation compensation circuit for FETS 失效
标题翻译： FETS的阈值电压波动补偿电路
公开(公告)号：US4857769A
公开(公告)日：1989-08-15
申请号：US143385
申请日：1988-01-13
申请人： Nobuo Kotera , Kiichi Yamashita , Taizo Kinoshita , Hirotoshi Tanaka , Satoshi Tanaka , Minoru Nagata
发明人： Nobuo Kotera , Kiichi Yamashita , Taizo Kinoshita , Hirotoshi Tanaka , Satoshi Tanaka , Minoru Nagata
IPC分类号： H03K19/003
CPC分类号： H03K19/00384
摘要： This invention relates to a threshold voltage detection circuit for detecting the threshold voltage of field effect transistors (FETs) and to a semiconductor circuit capable of a stable operation irrespective of the fluctuation of the threshold voltage by utilizing this threshold voltage detection circuit. The source-drain path of first FET is connected in series with that of second FET having substantially the same threshold voltage as that of the first FET and the conductances of these first and second FETs are set to a predetermined ratio to generate a voltage drop associated with the threshold voltage in the first FET. This voltage drop can be used for detecting the threshold voltage and for level-shifting. The output of the series connection of the first and second FETs is applied to the gate of a constant current FET having the same threshold voltage as that of the first and second FETs and the drain current of the constant current FET can thus be set irrespective of the fluctuation of the threshold voltage.
摘要翻译：本发明涉及一种阈值电压检测电路，用于通过利用该阈值电压检测电路来检测场效应晶体管（FET）的阈值电压和能够稳定工作的半导体电路，而与阈值电压的波动无关。第一FET的源极 - 漏极路径与具有与第一FET基本相同的阈值电压的第二FET的源极 - 漏极路径串联连接，并且将这些第一和第二FET的电导设置为预定的比率以产生相关的电压降与第一FET中的阈值电压。该电压降可用于检测阈值电压和电平转换。第一和第二FET的串联连接的输出被施加到具有与第一和第二FET相同的阈值电压的恒流FET的栅极，因此可以设定恒定电流FET的漏极电流，而不管阈值电压的波动。

2. 发明授权

US4847550A Semiconductor circuit 失效
标题翻译：半导体电路
公开(公告)号：US4847550A
公开(公告)日：1989-07-11
申请号：US143802
申请日：1988-01-14
申请人： Satoshi Tanaka , Hirotoshi Tanaka , Taizo Kinoshita , Nobuo Kotera , Minoru Nagata , Kiichi Yamashita , Tomoyuki Watanabe
发明人： Satoshi Tanaka , Hirotoshi Tanaka , Taizo Kinoshita , Nobuo Kotera , Minoru Nagata , Kiichi Yamashita , Tomoyuki Watanabe
IPC分类号： G05F3/24
CPC分类号： G05F3/245 , G05F3/247
摘要： A constant voltage circuit according to this invention comprises first means attenuating or dividing fluctuating voltage and an amplifying FET, to the gate of which the output attenuated or divided by the first means is applied and whose drain is connected with the fluctuating voltage through load means. The attenuation ratio or division ratio of the first means, the mutual conductance of the amplifying FET and the impedance of the load means are so set that the voltage drop across the load means cancels the fluctuating amount of the fluctuating voltage. Consequently an output voltage, which is maintained substantially constant, is obtained at the drain of the amplifying FET, independently of fluctuations in the fluctuating voltage, and thus a constant voltage circuit can be obtained. A constant current circuit according to this invention utilizes the constant voltage circuit described above. The output voltage of the constant voltage circuit is supplied to the gate of the constant current FET. Consequently a current, which is maintained substantially constant, flows through the drain-source path of this constant current FET and thus a constant current circuit can be obtained.

3. 发明授权

US4825145A Constant current circuit 失效
标题翻译：恒流电路
公开(公告)号：US4825145A
公开(公告)日：1989-04-25
申请号：US133914
申请日：1987-12-16
申请人： Hirotoshi Tanaka , Satoshi Tanaka , Taizo Kinoshita , Nobuo Kotera , Minoru Nagata
发明人： Hirotoshi Tanaka , Satoshi Tanaka , Taizo Kinoshita , Nobuo Kotera , Minoru Nagata
IPC分类号： G05F3/24
CPC分类号： G05F3/247
摘要： A constant current circuit includes a first FET providing an input reference current flow, a second FET providing an output current flow and a non-linear impedance element connected between the drain and the gate of the first FET. By setting a parameter of the non-linear impedance element and a parameter of the first FET to have a specific relationship with each other, the output current can be maintained at a substantially definite value irrespective of relatively large variations of the input reference current.
摘要翻译：恒流电路包括提供输入参考电流的第一FET，提供输出电流的第二FET和连接在第一FET的漏极和栅极之间的非线性阻抗元件。通过将非线性阻抗元件的参数和第一FET的参数设置为具有特定的关系，输出电流可以保持在基本上确定的值，而与输入参考电流的相对大的变化无关。

4. 发明授权

US4881044A Amplifying circuit 失效
标题翻译：放大电路
公开(公告)号：US4881044A
公开(公告)日：1989-11-14
申请号：US139790
申请日：1987-12-30
申请人： Taizo Kinoshita , Satoshi Tanaka , Hirotoshi Tanaka , Nobuo Kotera , Minoru Nagata
发明人： Taizo Kinoshita , Satoshi Tanaka , Hirotoshi Tanaka , Nobuo Kotera , Minoru Nagata
IPC分类号： H03F3/45
CPC分类号： H03F3/45385
摘要： A wide-band and high-gain differential amplifier adapted to amplifying transmitted optical signals of the GHz band is constituted by GaAs MESFET's.Two MESFET's Q1 and Q2 are differentially connected to each other. Drains of Q1 and Q2 are connected to load resistances R.sub.L and R.sub.L via a source-drain path of other MESFET's Q3 and Q4 whose gates are grounded in AC-wise.Current by-passing means 4, 4 are connected to the sources of other MESFET's Q3, Q4. DC bias currents of the differential pair of MESFET's Q1, Q2 are set to relatively large values to increase the mutual conductance gm of the differential pair of MESFET's Q1, Q2. Despite a large DC bias current, the current by-passing means 4, 4 decrease the DC voltage drops across the load resistances R.sub.L, R.sub.L, and enable the differntial amplifier to operate on a low power source voltage.

5. 发明授权

US5166553A Current mirror circuit employing depletion mode FETs 失效
标题翻译：采用耗尽型FET的电流镜电路
公开(公告)号：US5166553A
公开(公告)日：1992-11-24
申请号：US364461
申请日：1989-06-12
申请人： Nobuo Kotera , Kiichi Yamashita , Hirotoshi Tanaka , Satoshi Tanaka , Yasushi Hatta , Minoru Nagata
发明人： Nobuo Kotera , Kiichi Yamashita , Hirotoshi Tanaka , Satoshi Tanaka , Yasushi Hatta , Minoru Nagata
IPC分类号： G05F3/24 , G05F3/26 , H03F3/34 , H03F3/343 , H03F3/347 , H03K17/14
CPC分类号： H03K17/145 , G05F3/262
摘要： A semiconductor circuit including first and second FET's for delivering an output signal without being affected by a change in threshold voltage of the FET's is disclosed. According to one practical form of the semiconductor circuit, the drain-source current path of an additional FET whose gate and source are shorted to each other, is connected in parallel to the drain-source current path of the first FET whose gate and drain are shorted to each other, to make the voltage-current characteristic of the second FET agree with that of the parallel combination of the first and additional FET's. According to another practical form of the semiconductor circuit, a voltage dividing circuit is connected in parallel to the drain-source current path of the first FET, and a divided output voltage from the voltage dividing circuit is applied between the gate and source of each of the first and second FET's.
摘要翻译：公开了一种包括用于传递输出信号而不受FET的阈值电压变化影响的第一和第二FET的半导体电路。根据半导体电路的一种实际形式，其栅极和源极彼此短路的附加FET的漏极 - 源极电流路径并联连接到栅极和漏极的第一FET的漏极 - 源极电流路径使第二FET的电压 - 电流特性与第一和另外的FET的并联组合一致。根据半导体电路的另一种实际形式，分压电路并联连接到第一FET的漏极 - 源极电流路径，并且来自分压电路的分压输出电压施加在每个的栅极和源极之间第一和第二FET。

6. 发明授权

US4968904A MESFET circuit with threshold-compensated source-follower output 失效
标题翻译：具有阈值补偿源跟随器输出的MESFET电路
公开(公告)号：US4968904A
公开(公告)日：1990-11-06
申请号：US323947
申请日：1989-03-15
申请人： Kiichi Yamashita , Keiichi Kitamura , Nobuo Kotera , Yasushi Hatta , Hiroyuki Tanaka
发明人： Kiichi Yamashita , Keiichi Kitamura , Nobuo Kotera , Yasushi Hatta , Hiroyuki Tanaka
IPC分类号： H03K19/0952 , H01L27/095 , H03K19/003 , H03K19/094
CPC分类号： H03K19/00384 , H03K19/09436
摘要： A logic circuit made up of FET's is disclosed in which an output interface circuit is formed of a source follower circuit including a signal transmitting FET and a constant-current supplying FET, and a ratio of the gate width of the signal transmitting FET to the gate width of the constant-current supplying FET is set so that the high and low levels of the output signal of the logic circuit are independent of the threshold voltage of the FET's.
摘要翻译：公开了一种由FET构成的逻辑电路，其中输出接口电路由包括信号发送FET和恒流供应FET的源极跟随器电路以及信号发送FET的栅极宽度与栅极的比率设定恒流供给FET的宽度，使得逻辑电路的输出信号的高电平和低电平独立于FET的阈值电压。

7. 发明授权

US5132752A Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US5132752A
公开(公告)日：1992-07-21
申请号：US658463
申请日：1991-02-22
申请人： Yasunari Umemoto , Nobuo Kotera , Kiichi Ueyanagi , Norikazu Hashimoto , Nobutoshi Matsunaga , Yasuo Wada , Shoji Shukuri , Noboru Masuda , Takehisa Hayashi , Hirotoshi Tanaka
发明人： Yasunari Umemoto , Nobuo Kotera , Kiichi Ueyanagi , Norikazu Hashimoto , Nobutoshi Matsunaga , Yasuo Wada , Shoji Shukuri , Noboru Masuda , Takehisa Hayashi , Hirotoshi Tanaka
IPC分类号： H01L29/10 , H01L29/812
CPC分类号： H01L29/1075 , H01L29/812 , Y10S257/903
摘要： A field effect transistor formed on a semi-insulator or compound semiconductor substrate comprises a first semiconductor layer forming a source region, a drain region and a channel layer, and a second semiconductor layer having a reverse conduction type to that of the first semiconductor layer. The second semiconductor layer is doped so that it will be totally depleted. Therefore, a portion of the second semiconductor layer adjacent to the substrate will remain conductive. The field effect transistor with this structure prevents the short channel effect and the soft error due to .alpha.-particles. A threshold voltage control arrangement is also provided using the feature of a control electrode coupled to the second semiconductor layer and a feedback arrangement.
摘要翻译：形成在半绝缘体或化合物半导体衬底上的场效应晶体管包括形成源极区，漏极区和沟道层的第一半导体层以及具有与第一半导体层相反的导通型的第二半导体层。第二半导体层被掺杂以使其完全耗尽。因此，与衬底相邻的第二半导体层的一部分将保持导电。具有这种结构的场效应晶体管防止短沟道效应和由于α-粒子引起的软误差。还使用耦合到第二半导体层的控制电极的特征和反馈装置来提供阈值电压控制装置。

8. 发明授权

US4518868A Superconductive large-scale integrated circuit chip 失效
标题翻译：超导大型集成电路芯片
公开(公告)号：US4518868A
公开(公告)日：1985-05-21
申请号：US278730
申请日：1981-06-29
申请人： Yutaka Harada , Kunio Yamashita , Nobuo Kotera , Hirotoshi Tanaka
发明人： Yutaka Harada , Kunio Yamashita , Nobuo Kotera , Hirotoshi Tanaka
IPC分类号： H01L27/18 , H01L39/02 , H01L39/22 , H03K17/92 , H03K19/195
CPC分类号： H03K17/92 , H01L27/18 , H01L39/025 , Y10S505/865
摘要： A superconductive large-scale integrated circuit chip comprises a plurality of pads, a superconductive line which short-circuits respectively adjacent pairs of the pads, and an input buffer circuit. The input buffer circuit includes a Josephson junction which is either in a superconducting state or a finite voltage state in response to a magnetic field established by current that is supplied to the superconductive line by flowing in from one of the two pads and flowing out from the other pad. The input buffer circuit wave-shapes the externally supplied signal into an amplitude-controlled signal, and the latter signal is led by a superconductive line to a circuit within the chip which requires the signal. Even when the external signal current has become abnormally great due to noise, etc., any circuit situated halfway within the chip can be prevented from malfunctioning from the magnetic flux generated by the large current.
摘要翻译：超导大规模集成电路芯片包括多个焊盘，分别相邻焊盘对短路的超导线和输入缓冲电路。输入缓冲电路包括约瑟夫逊结，其响应于由电流建立的磁场处于超导状态或有限电压状态，该电流通过从两个焊盘中的一个流入并从其中流出而被提供给超导线其他垫输入缓冲器电路将外部提供的信号波形成幅度控制信号，后一个信号由超导线引导到需要信号的芯片内的电路。即使当外部信号电流由于噪声等而变得异常大时，可以防止位于芯片中间的任何电路从由大电流产生的磁通发生故障。

9. 发明授权

US4223292A Hall element 失效
标题翻译：霍尔元件
公开(公告)号：US4223292A
公开(公告)日：1980-09-16
申请号：US927392
申请日：1978-07-24
申请人： Juichi Morikawa , Nobuo Kotera
发明人： Juichi Morikawa , Nobuo Kotera
IPC分类号： H01L43/06 , H01L43/04
CPC分类号： H01L43/065
摘要： A basically cross-shaped semiconductor Hall element comprises a pair of current-supplying electrodes as well as a pair of Hall electrodes. The structure includes trapezoidal semiconductor regions extending from the central magneto-sensitive region in both the current-supplying electrode directions to thereby suppress the element temperature rise due to Joule heating. In addition, the contiguous slant edges of the extended trapezoidal portion form an angle .theta. greater than 90.degree. with lateral edges of the central rectangular magneto-sensitive region to thereby suppress the semiconductor noise dependent on the shape itself.
摘要翻译：基本上十字形的半导体霍尔元件包括一对供电电极以及一对霍尔电极。该结构包括从供电电极方向上的中央磁敏区域延伸的梯形半导体区域，从而抑制由于焦耳加热引起的元件温度升高。此外，延伸梯形部分的连续倾斜边缘与中心矩形磁敏区域的横向边缘形成大于90°的角度θ，从而根据形状本身抑制半导体噪声。

10. 发明授权

US4672244A Josephson logic integrated circuit 失效
标题翻译：约瑟夫森逻辑集成电路
公开(公告)号：US4672244A
公开(公告)日：1987-06-09
申请号：US782185
申请日：1985-09-30
申请人： Yutaka Harada , Ushio Kawabe , Nobuo Kotera , Atsushi Asano
发明人： Yutaka Harada , Ushio Kawabe , Nobuo Kotera , Atsushi Asano
IPC分类号： H01L39/02 , H03K17/92 , H03K19/195
CPC分类号： H03K19/1952 , H03K17/92 , H03K19/195 , H03K19/1956 , Y10S505/858
摘要： A Josephson logic integrated circuit packaged on a single substrate, wherein a portion for delivering an output out of the integrated circuit is constructed of an A.C.-driven Josephson logic circuit, and a portion for driving the internal part of the integrated circuit is constructed of a D.C.-driven Josephson logic circuit.
摘要翻译：封装在单个基板上的约瑟夫森逻辑集成电路，其中用于将集成电路输出的输出部分由AC驱动的约瑟夫森逻辑电路构成，并且用于驱动集成电路的内部的部分由约瑟夫森直流驱动逻辑电路。

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